Lines Matching refs:add_boot_arg

100 add_boot_arg(u32 **boot_conf, u32 param, u32 data)  in add_boot_arg()  function
221 add_boot_arg(&boot_conf, register_offset, in meta_ldr_cmd_config()
351 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_BASE(seg_id), seg_base); in configure_seg_id()
352 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_LIMIT(seg_id), limit_off); in configure_seg_id()
353 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA0(seg_id), seg_out_addr0); in configure_seg_id()
354 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA1(seg_id), seg_out_addr1); in configure_seg_id()
426 add_boot_arg(&boot_conf, META_CR_MMCU_LOCAL_EBCTRL, in configure_meta_caches()
431 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(0), d_cache_t0); in configure_meta_caches()
432 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(1), d_cache_t1); in configure_meta_caches()
433 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(2), d_cache_t2); in configure_meta_caches()
434 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(3), d_cache_t3); in configure_meta_caches()
437 add_boot_arg(&boot_conf, META_CR_MMCU_DCACHE_CTRL, in configure_meta_caches()
441 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(0), i_cache_t0); in configure_meta_caches()
442 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(1), i_cache_t1); in configure_meta_caches()
443 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(2), i_cache_t2); in configure_meta_caches()
444 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(3), i_cache_t3); in configure_meta_caches()
447 add_boot_arg(&boot_conf, META_CR_MMCU_ICACHE_CTRL, in configure_meta_caches()
450 add_boot_arg(&boot_conf, 0x040000C0, 0); in configure_meta_caches()
467 add_boot_arg(&boot_conf, META_CR_SYSC_JTAG_THREAD, in pvr_meta_fw_process()
481 add_boot_arg(&boot_conf, 0, 0); in pvr_meta_fw_process()
487 add_boot_arg(&boot_conf, core_code_fw_addr, core_code_alloc_size); in pvr_meta_fw_process()
489 add_boot_arg(&boot_conf, 0, 0); in pvr_meta_fw_process()
492 add_boot_arg(&boot_conf, 0, 0); in pvr_meta_fw_process()