Lines Matching +full:0 +full:x1ff
10 #define BUNIT_REG_BISOC 0x11
13 #define _SSPM0_SSC(val) ((val) << 0)
14 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
15 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
16 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
17 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
18 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
20 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
21 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
22 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
23 #define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
24 #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
28 #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
30 #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
31 #define SSPM1_FREQ_SHIFT 0
32 #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
34 #define PUNIT_REG_VEDSSPM0 0x32
35 #define PUNIT_REG_VEDSSPM1 0x33
37 #define PUNIT_REG_DSPSSPM 0x36
39 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
41 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
43 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
45 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
50 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
51 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
52 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
53 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
54 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
56 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
57 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
58 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
59 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
60 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
62 #define PUNIT_REG_ISPSSPM0 0x39
63 #define PUNIT_REG_ISPSSPM1 0x3a
65 #define PUNIT_REG_PWRGT_CTRL 0x60
66 #define PUNIT_REG_PWRGT_STATUS 0x61
68 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
73 #define PUNIT_PWGT_IDX_RENDER 0
85 #define PUNIT_REG_GPU_LFM 0xd3
86 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
87 #define PUNIT_REG_GPU_FREQ_STS 0xd8
89 #define GENFREQSTATUS (1 << 0)
90 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
91 #define PUNIT_REG_CZ_TIMESTAMP 0xce
93 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
94 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
96 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
97 #define FB_GFX_FREQ_FUSE_MASK 0xff
102 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
105 #define PUNIT_REG_DDR_SETUP2 0x139
108 #define FORCE_DDR_HIGH_FREQ (1 << 0)
110 #define PUNIT_GPU_STATUS_REG 0xdb
112 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
114 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
116 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
118 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
120 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
122 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
124 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
125 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
126 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
127 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
129 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
131 #define VLV_TURBO_SOC_OVERRIDE 0x04
138 #define CCK_FUSE_REG 0x8
139 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
140 #define CCK_REG_DSI_PLL_FUSE 0x44
141 #define CCK_REG_DSI_PLL_CONTROL 0x48
145 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
149 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
151 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
153 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
158 #define DSI_PLL_LOCK (1 << 0)
159 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
165 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
168 #define DSI_PLL_M1_DIV_SHIFT 0
169 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
170 #define CCK_CZ_CLOCK_CONTROL 0x62
171 #define CCK_GPLL_CLOCK_CONTROL 0x67
172 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
173 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
176 #define CCK_FREQUENCY_STATUS (0x1f << 8)
178 #define CCK_FREQUENCY_VALUES (0x1f << 0)