2  * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 		return -ENOMEM;  in alloc_empty_config()
28 	oa_config->perf = perf;  in alloc_empty_config()
29 	kref_init(&oa_config->ref);  in alloc_empty_config()
31 	strscpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid));  in alloc_empty_config()
33 	mutex_lock(&perf->metrics_lock);  in alloc_empty_config()
35 	oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL);  in alloc_empty_config()
36 	if (oa_config->id < 0)  {  in alloc_empty_config()
37 		mutex_unlock(&perf->metrics_lock);  in alloc_empty_config()
39 		return -ENOMEM;  in alloc_empty_config()
42 	mutex_unlock(&perf->metrics_lock);  in alloc_empty_config()
53 	mutex_lock(&perf->metrics_lock);  in destroy_empty_config()
55 	idr_for_each_entry(&perf->metrics_idr, tmp, id) {  in destroy_empty_config()
56 		if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {  in destroy_empty_config()
63 		idr_remove(&perf->metrics_idr, oa_config->id);  in destroy_empty_config()
65 	mutex_unlock(&perf->metrics_lock);  in destroy_empty_config()
77 	mutex_lock(&perf->metrics_lock);  in get_empty_config()
79 	idr_for_each_entry(&perf->metrics_idr, tmp, id) {  in get_empty_config()
80 		if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {  in get_empty_config()
86 	mutex_unlock(&perf->metrics_lock);  in get_empty_config()
97 		.engine = intel_engine_lookup_user(perf->i915,  in test_stream()
101 		.oa_format = GRAPHICS_VER(perf->i915) == 12 ?  in test_stream()
110 	gt = props.engine->gt;  in test_stream()
115 	props.metrics_set = oa_config->id;  in test_stream()
123 	stream->perf = perf;  in test_stream()
125 	mutex_lock(&gt->perf.lock);  in test_stream()
130 	mutex_unlock(&gt->perf.lock);  in test_stream()
139 	struct intel_gt *gt = stream->engine->gt;  in stream_destroy()
141 	mutex_lock(&gt->perf.lock);  in stream_destroy()
143 	mutex_unlock(&gt->perf.lock);  in stream_destroy()
153 	stream = test_stream(&i915->perf);  in live_sanitycheck()
155 		return -EINVAL;  in live_sanitycheck()
163 	u32 *cs;  in write_timestamp()  local
166 	cs = intel_ring_begin(rq, 6);  in write_timestamp()
167 	if (IS_ERR(cs))  in write_timestamp()
168 		return PTR_ERR(cs);  in write_timestamp()
171 	if (GRAPHICS_VER(rq->i915) >= 8)  in write_timestamp()
174 	*cs++ = GFX_OP_PIPE_CONTROL(len);  in write_timestamp()
175 	*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB |  in write_timestamp()
178 	*cs++ = slot * sizeof(u32);  in write_timestamp()
179 	*cs++ = 0;  in write_timestamp()
180 	*cs++ = 0;  in write_timestamp()
181 	*cs++ = 0;  in write_timestamp()
183 	intel_ring_advance(rq, cs);  in write_timestamp()
190 	while (!intel_read_status_page(rq->engine, slot) &&  in poll_status()
210 	stream = test_stream(&i915->perf);  in live_noa_delay()
212 		return -ENOMEM;  in live_noa_delay()
214 	expected = atomic64_read(&stream->perf->noa_programming_delay);  in live_noa_delay()
216 	if (stream->engine->class != RENDER_CLASS) {  in live_noa_delay()
217 		err = -ENODEV;  in live_noa_delay()
222 		intel_write_status_page(stream->engine, 0x100 + i, 0);  in live_noa_delay()
224 	rq = intel_engine_create_kernel_request(stream->engine);  in live_noa_delay()
230 	if (rq->engine->emit_init_breadcrumb) {  in live_noa_delay()
231 		err = rq->engine->emit_init_breadcrumb(rq);  in live_noa_delay()
244 	err = rq->engine->emit_bb_start(rq,  in live_noa_delay()
245 					i915_ggtt_offset(stream->noa_wait), 0,  in live_noa_delay()
269 	delay = intel_read_status_page(stream->engine, 0x102);  in live_noa_delay()
270 	delay -= intel_read_status_page(stream->engine, 0x100);  in live_noa_delay()
271 	delay = intel_gt_clock_interval_to_ns(stream->engine->gt, delay);  in live_noa_delay()
275 	if (4 * delay < 3 * expected || 2 * delay > 3 * expected) {  in live_noa_delay()
280 		err = -EINVAL;  in live_noa_delay()
295 	u32 *cs, *store;  in live_noa_gpr()  local
303 	stream = test_stream(&i915->perf);  in live_noa_gpr()
305 		return -ENOMEM;  in live_noa_gpr()
307 	gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));  in live_noa_gpr()
309 	ce = intel_context_create(stream->engine);  in live_noa_gpr()
315 	/* Poison the ce->vm so we detect writes not to the GGTT gt->scratch */  in live_noa_gpr()
316 	scratch = __px_vaddr(ce->vm->scratch[0]);  in live_noa_gpr()
326 	if (rq->engine->emit_init_breadcrumb) {  in live_noa_gpr()
327 		err = rq->engine->emit_init_breadcrumb(rq);  in live_noa_gpr()
335 	cs = intel_ring_begin(rq, 2 * 32 + 2);  in live_noa_gpr()
336 	if (IS_ERR(cs)) {  in live_noa_gpr()
337 		err = PTR_ERR(cs);  in live_noa_gpr()
342 	*cs++ = MI_LOAD_REGISTER_IMM(32);  in live_noa_gpr()
344 		*cs++ = gpr0 + i * sizeof(u32);  in live_noa_gpr()
345 		*cs++ = STACK_MAGIC;  in live_noa_gpr()
347 	*cs++ = MI_NOOP;  in live_noa_gpr()
348 	intel_ring_advance(rq, cs);  in live_noa_gpr()
351 	err = rq->engine->emit_bb_start(rq,  in live_noa_gpr()
352 					i915_ggtt_offset(stream->noa_wait), 0,  in live_noa_gpr()
360 	store = memset32(rq->engine->status_page.addr + 512, 0, 32);  in live_noa_gpr()
364 		cs = intel_ring_begin(rq, 4);  in live_noa_gpr()
365 		if (IS_ERR(cs)) {  in live_noa_gpr()
366 			err = PTR_ERR(cs);  in live_noa_gpr()
376 		*cs++ = cmd;  in live_noa_gpr()
377 		*cs++ = gpr0 + i * sizeof(u32);  in live_noa_gpr()
378 		*cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +  in live_noa_gpr()
381 		*cs++ = 0;  in live_noa_gpr()
382 		intel_ring_advance(rq, cs);  in live_noa_gpr()
387 	if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, HZ / 2) < 0) {  in live_noa_gpr()
389 		intel_gt_set_wedged(stream->engine->gt);  in live_noa_gpr()
390 		err = -EIO;  in live_noa_gpr()
401 		err = -EINVAL;  in live_noa_gpr()
408 		err = -EINVAL;  in live_noa_gpr()
427 	struct i915_perf *perf = &i915->perf;  in i915_perf_live_selftests()
430 	if (!perf->metrics_kobj || !perf->ops.enable_metric_set)  in i915_perf_live_selftests()
436 	err = alloc_empty_config(&i915->perf);  in i915_perf_live_selftests()
442 	destroy_empty_config(&i915->perf);  in i915_perf_live_selftests()