Lines Matching +full:0 +full:xcfff
67 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
116 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) in intel_uncore_forcewake_domain_to_str()
138 fw_clear(d, 0xefff); in fw_domain_reset()
140 fw_clear(d, 0xffff); in fw_domain_reset()
168 return __wait_for_ack(d, ack, 0); in wait_ack_clear()
184 if (fw_ack(d) == ~0) { in fw_domain_wait_ack_clear()
186 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n", in fw_domain_wait_ack_clear()
199 ACK_CLEAR = 0,
208 const u32 value = type == ACK_SET ? ack_bit : 0; in fw_domain_wait_ack_with_fallback()
241 "%s had to use fallback to %s ack, 0x%x (passes %u)\n", in fw_domain_wait_ack_with_fallback()
247 return ack_detected ? 0 : -ETIMEDOUT; in fw_domain_wait_ack_with_fallback()
375 * w/a for a sporadic read returning 0 by waiting for the GT in __gen6_gt_wait_for_thread_c0()
379 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), in __gen6_gt_wait_for_thread_c0()
441 if (--domain->wake_count == 0) in intel_uncore_fw_release_timer()
467 active_domains = 0; in intel_uncore_forcewake_reset()
471 if (hrtimer_cancel(&domain->timer) == 0) in intel_uncore_forcewake_reset()
484 if (active_domains == 0) in intel_uncore_forcewake_reset()
487 if (--retry_count == 0) { in intel_uncore_forcewake_reset()
522 * reads will come back with 0xFFFFFFFF for every register and things in fpga_check_for_unclaimed_mmio()
528 * bits that will always read back as 0's so we can use them as canaries in fpga_check_for_unclaimed_mmio()
531 if (unlikely(dbg == ~0)) in fpga_check_for_unclaimed_mmio()
533 "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n"); in fpga_check_for_unclaimed_mmio()
562 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg); in gen6_check_for_fifo_debug()
911 __reg < 0x40000 || __reg >= 0x116000; \
921 return 0; in fw_range_cmp()
926 unsigned int start__ = 0, end__ = (num); \
931 if (ret__ < 0) { \
933 } else if (ret__ > 0) { \
957 return 0; in find_fw_domain()
968 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", in find_fw_domain()
995 { .start = 0x2030, .end = 0x2030 },
996 { .start = 0xA008, .end = 0xA00C },
997 { .start = 0x12030, .end = 0x12030 },
998 { .start = 0x1a030, .end = 0x1a030 },
999 { .start = 0x22030, .end = 0x22030 },
1003 { .start = 0x2030, .end = 0x2030 },
1004 { .start = 0x2550, .end = 0x2550 },
1005 { .start = 0xA008, .end = 0xA00C },
1006 { .start = 0x22030, .end = 0x22030 },
1007 { .start = 0x22230, .end = 0x22230 },
1008 { .start = 0x22510, .end = 0x22550 },
1009 { .start = 0x1C0030, .end = 0x1C0030 },
1010 { .start = 0x1C0230, .end = 0x1C0230 },
1011 { .start = 0x1C0510, .end = 0x1C0550 },
1012 { .start = 0x1C4030, .end = 0x1C4030 },
1013 { .start = 0x1C4230, .end = 0x1C4230 },
1014 { .start = 0x1C4510, .end = 0x1C4550 },
1015 { .start = 0x1C8030, .end = 0x1C8030 },
1016 { .start = 0x1C8230, .end = 0x1C8230 },
1017 { .start = 0x1C8510, .end = 0x1C8550 },
1018 { .start = 0x1D0030, .end = 0x1D0030 },
1019 { .start = 0x1D0230, .end = 0x1D0230 },
1020 { .start = 0x1D0510, .end = 0x1D0550 },
1021 { .start = 0x1D4030, .end = 0x1D4030 },
1022 { .start = 0x1D4230, .end = 0x1D4230 },
1023 { .start = 0x1D4510, .end = 0x1D4550 },
1024 { .start = 0x1D8030, .end = 0x1D8030 },
1025 { .start = 0x1D8230, .end = 0x1D8230 },
1026 { .start = 0x1D8510, .end = 0x1D8550 },
1030 { .start = 0x2030, .end = 0x2030 },
1031 { .start = 0x2510, .end = 0x2550 },
1032 { .start = 0xA008, .end = 0xA00C },
1033 { .start = 0xA188, .end = 0xA188 },
1034 { .start = 0xA278, .end = 0xA278 },
1035 { .start = 0xA540, .end = 0xA56C },
1036 { .start = 0xC4C8, .end = 0xC4C8 },
1037 { .start = 0xC4D4, .end = 0xC4D4 },
1038 { .start = 0xC600, .end = 0xC600 },
1039 { .start = 0x22030, .end = 0x22030 },
1040 { .start = 0x22510, .end = 0x22550 },
1041 { .start = 0x1C0030, .end = 0x1C0030 },
1042 { .start = 0x1C0510, .end = 0x1C0550 },
1043 { .start = 0x1C4030, .end = 0x1C4030 },
1044 { .start = 0x1C4510, .end = 0x1C4550 },
1045 { .start = 0x1C8030, .end = 0x1C8030 },
1046 { .start = 0x1C8510, .end = 0x1C8550 },
1047 { .start = 0x1D0030, .end = 0x1D0030 },
1048 { .start = 0x1D0510, .end = 0x1D0550 },
1049 { .start = 0x1D4030, .end = 0x1D4030 },
1050 { .start = 0x1D4510, .end = 0x1D4550 },
1051 { .start = 0x1D8030, .end = 0x1D8030 },
1052 { .start = 0x1D8510, .end = 0x1D8550 },
1059 { .start = 0x1E0030, .end = 0x1E0030 },
1060 { .start = 0x1E0510, .end = 0x1E0550 },
1061 { .start = 0x1E4030, .end = 0x1E4030 },
1062 { .start = 0x1E4510, .end = 0x1E4550 },
1063 { .start = 0x1E8030, .end = 0x1E8030 },
1064 { .start = 0x1E8510, .end = 0x1E8550 },
1065 { .start = 0x1F0030, .end = 0x1F0030 },
1066 { .start = 0x1F0510, .end = 0x1F0550 },
1067 { .start = 0x1F4030, .end = 0x1F4030 },
1068 { .start = 0x1F4510, .end = 0x1F4550 },
1069 { .start = 0x1F8030, .end = 0x1F8030 },
1070 { .start = 0x1F8510, .end = 0x1F8550 },
1074 { .start = 0x2030, .end = 0x2030 },
1075 { .start = 0x2510, .end = 0x2550 },
1076 { .start = 0xA008, .end = 0xA00C },
1077 { .start = 0xA188, .end = 0xA188 },
1078 { .start = 0xA278, .end = 0xA278 },
1079 { .start = 0xA540, .end = 0xA56C },
1080 { .start = 0xC4C8, .end = 0xC4C8 },
1081 { .start = 0xC4E0, .end = 0xC4E0 },
1082 { .start = 0xC600, .end = 0xC600 },
1083 { .start = 0xC658, .end = 0xC658 },
1084 { .start = 0x22030, .end = 0x22030 },
1085 { .start = 0x22510, .end = 0x22550 },
1086 { .start = 0x1C0030, .end = 0x1C0030 },
1087 { .start = 0x1C0510, .end = 0x1C0550 },
1088 { .start = 0x1C4030, .end = 0x1C4030 },
1089 { .start = 0x1C4510, .end = 0x1C4550 },
1090 { .start = 0x1C8030, .end = 0x1C8030 },
1091 { .start = 0x1C8510, .end = 0x1C8550 },
1092 { .start = 0x1D0030, .end = 0x1D0030 },
1093 { .start = 0x1D0510, .end = 0x1D0550 },
1094 { .start = 0x1D4030, .end = 0x1D4030 },
1095 { .start = 0x1D4510, .end = 0x1D4550 },
1096 { .start = 0x1D8030, .end = 0x1D8030 },
1097 { .start = 0x1D8510, .end = 0x1D8550 },
1098 { .start = 0x1E0030, .end = 0x1E0030 },
1099 { .start = 0x1E0510, .end = 0x1E0550 },
1100 { .start = 0x1E4030, .end = 0x1E4030 },
1101 { .start = 0x1E4510, .end = 0x1E4550 },
1102 { .start = 0x1E8030, .end = 0x1E8030 },
1103 { .start = 0x1E8510, .end = 0x1E8550 },
1104 { .start = 0x1F0030, .end = 0x1F0030 },
1105 { .start = 0x1F0510, .end = 0x1F0550 },
1106 { .start = 0x1F4030, .end = 0x1F4030 },
1107 { .start = 0x1F4510, .end = 0x1F4550 },
1108 { .start = 0x1F8030, .end = 0x1F8030 },
1109 { .start = 0x1F8510, .end = 0x1F8550 },
1113 { .start = 0x2030, .end = 0x2030 },
1114 { .start = 0x2510, .end = 0x2550 },
1115 { .start = 0xA008, .end = 0xA00C },
1116 { .start = 0xA188, .end = 0xA188 },
1117 { .start = 0xA278, .end = 0xA278 },
1118 { .start = 0xA540, .end = 0xA56C },
1119 { .start = 0xC050, .end = 0xC050 },
1120 { .start = 0xC340, .end = 0xC340 },
1121 { .start = 0xC4C8, .end = 0xC4C8 },
1122 { .start = 0xC4E0, .end = 0xC4E0 },
1123 { .start = 0xC600, .end = 0xC600 },
1124 { .start = 0xC658, .end = 0xC658 },
1125 { .start = 0xCFD4, .end = 0xCFDC },
1126 { .start = 0x22030, .end = 0x22030 },
1127 { .start = 0x22510, .end = 0x22550 },
1131 { .start = 0x1C0030, .end = 0x1C0030 },
1132 { .start = 0x1C0510, .end = 0x1C0550 },
1133 { .start = 0x1C8030, .end = 0x1C8030 },
1134 { .start = 0x1C8510, .end = 0x1C8550 },
1135 { .start = 0x1D0030, .end = 0x1D0030 },
1136 { .start = 0x1D0510, .end = 0x1D0550 },
1137 { .start = 0x38A008, .end = 0x38A00C },
1138 { .start = 0x38A188, .end = 0x38A188 },
1139 { .start = 0x38A278, .end = 0x38A278 },
1140 { .start = 0x38A540, .end = 0x38A56C },
1141 { .start = 0x38A618, .end = 0x38A618 },
1142 { .start = 0x38C050, .end = 0x38C050 },
1143 { .start = 0x38C340, .end = 0x38C340 },
1144 { .start = 0x38C4C8, .end = 0x38C4C8 },
1145 { .start = 0x38C4E0, .end = 0x38C4E4 },
1146 { .start = 0x38C600, .end = 0x38C600 },
1147 { .start = 0x38C658, .end = 0x38C658 },
1148 { .start = 0x38CFD4, .end = 0x38CFDC },
1158 return 0; in mmio_range_cmp()
1183 enum forcewake_domains __fwd = 0; \
1191 enum forcewake_domains __fwd = 0; \
1216 * 0x1000 - 0x1fff: GT
1217 * 0x2000 - 0x2cff: GT
1218 * 0x2d00 - 0x2fff: unused/reserved
1219 * 0x3000 - 0xffff: GT
1224 * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT)
1232 GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
1236 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1237 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
1238 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
1239 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1240 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
1241 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
1242 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1246 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1247 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1248 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1249 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1250 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1251 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1252 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1253 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1254 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1255 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1256 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1257 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1258 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1259 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1260 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1261 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1265 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
1266 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1267 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1268 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1269 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1270 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1271 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1272 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
1273 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1274 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1275 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1276 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1277 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1278 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1279 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
1280 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1281 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
1282 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1283 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1284 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1285 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
1286 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1287 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
1288 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1289 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
1290 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1291 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
1292 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1293 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
1294 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1295 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
1296 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1300 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
1301 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1302 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1303 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1304 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1305 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1306 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1307 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1308 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1309 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1310 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1311 GEN_FW_RANGE(0x8800, 0x8bff, 0),
1312 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1313 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
1314 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1315 GEN_FW_RANGE(0x9560, 0x95ff, 0),
1316 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
1317 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1318 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
1319 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1320 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
1321 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1322 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
1323 GEN_FW_RANGE(0x24000, 0x2407f, 0),
1324 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
1325 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
1326 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
1327 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
1328 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
1329 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1330 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1331 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1332 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
1333 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1334 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
1338 GEN_FW_RANGE(0x0, 0x1fff, 0), /*
1339 0x0 - 0xaff: reserved
1340 0xb00 - 0x1fff: always on */
1341 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1342 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT),
1343 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER),
1344 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT),
1345 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1346 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
1347 0x4000 - 0x48ff: gt
1348 0x4900 - 0x51ff: reserved */
1349 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
1350 0x5200 - 0x53ff: render
1351 0x5400 - 0x54ff: reserved
1352 0x5500 - 0x7fff: render */
1353 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1354 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1355 GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
1356 0x8160 - 0x817f: reserved
1357 0x8180 - 0x81ff: always on */
1358 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
1359 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1360 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
1361 0x8500 - 0x87ff: gt
1362 0x8800 - 0x8fff: reserved
1363 0x9000 - 0x947f: gt
1364 0x9480 - 0x94cf: reserved */
1365 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1366 GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
1367 0x9560 - 0x95ff: always on
1368 0x9600 - 0x97ff: reserved */
1369 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1370 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER),
1371 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /*
1372 0xb400 - 0xbf7f: gt
1373 0xb480 - 0xbfff: reserved
1374 0xc000 - 0xcfff: gt */
1375 GEN_FW_RANGE(0xd000, 0xd7ff, 0),
1376 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER),
1377 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT),
1378 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /*
1379 0xdc00 - 0xddff: render
1380 0xde00 - 0xde7f: reserved
1381 0xde80 - 0xe8ff: render
1382 0xe900 - 0xefff: reserved */
1383 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /*
1384 0xf000 - 0xffff: gt
1385 0x10000 - 0x147ff: reserved */
1386 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
1387 0x14800 - 0x14fff: render
1388 0x15000 - 0x16dff: reserved
1389 0x16e00 - 0x1bfff: render
1390 0x1c000 - 0x1ffff: reserved */
1391 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0),
1392 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2),
1393 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1394 GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1395 0x24000 - 0x2407f: always on
1396 0x24080 - 0x2417f: reserved */
1397 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
1398 0x24180 - 0x241ff: gt
1399 0x24200 - 0x249ff: reserved */
1400 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
1401 0x24a00 - 0x24a7f: render
1402 0x24a80 - 0x251ff: reserved */
1403 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /*
1404 0x25200 - 0x252ff: gt
1405 0x25300 - 0x255ff: reserved */
1406 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0),
1407 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /*
1408 0x25680 - 0x256ff: VD2
1409 0x25700 - 0x259ff: reserved */
1410 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0),
1411 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /*
1412 0x25a80 - 0x25aff: VD2
1413 0x25b00 - 0x2ffff: reserved */
1414 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1415 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1416 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1417 0x1c0000 - 0x1c2bff: VD0
1418 0x1c2c00 - 0x1c2cff: reserved
1419 0x1c2d00 - 0x1c2dff: VD0
1420 0x1c2e00 - 0x1c3eff: reserved
1421 0x1c3f00 - 0x1c3fff: VD0 */
1422 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1423 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1424 0x1c8000 - 0x1ca0ff: VE0
1425 0x1ca100 - 0x1cbeff: reserved
1426 0x1cbf00 - 0x1cbfff: VE0 */
1427 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
1428 0x1cc000 - 0x1ccfff: VD0
1429 0x1cd000 - 0x1cffff: reserved */
1430 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
1431 0x1d0000 - 0x1d2bff: VD2
1432 0x1d2c00 - 0x1d2cff: reserved
1433 0x1d2d00 - 0x1d2dff: VD2
1434 0x1d2e00 - 0x1d3eff: reserved
1435 0x1d3f00 - 0x1d3fff: VD2 */
1439 GEN_FW_RANGE(0x0, 0x1fff, 0), /*
1440 0x0 - 0xaff: reserved
1441 0xb00 - 0x1fff: always on */
1442 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1443 GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),
1444 GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
1445 0x4b00 - 0x4fff: reserved
1446 0x5000 - 0x51ff: always on */
1447 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1448 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1449 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1450 GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
1451 0x8160 - 0x817f: reserved
1452 0x8180 - 0x81ff: always on */
1453 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
1454 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1455 GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*
1456 0x8500 - 0x87ff: gt
1457 0x8800 - 0x8c7f: reserved
1458 0x8c80 - 0x8cff: gt (DG2 only) */
1459 GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*
1460 0x8d00 - 0x8dff: render (DG2 only)
1461 0x8e00 - 0x8fff: reserved */
1462 GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*
1463 0x9000 - 0x947f: gt
1464 0x9480 - 0x94cf: reserved */
1465 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1466 GEN_FW_RANGE(0x9560, 0x967f, 0), /*
1467 0x9560 - 0x95ff: always on
1468 0x9600 - 0x967f: reserved */
1469 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
1470 0x9680 - 0x96ff: render
1471 0x9700 - 0x97ff: reserved */
1472 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
1473 0x9800 - 0xb4ff: gt
1474 0xb500 - 0xbfff: reserved
1475 0xc000 - 0xcfff: gt */
1476 GEN_FW_RANGE(0xd000, 0xd7ff, 0),
1477 GEN_FW_RANGE(0xd800, 0xd87f, FORCEWAKE_RENDER),
1478 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT),
1479 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
1480 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
1481 0xdd00 - 0xddff: gt
1482 0xde00 - 0xde7f: reserved */
1483 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
1484 0xde80 - 0xdfff: render
1485 0xe000 - 0xe0ff: reserved
1486 0xe100 - 0xe8ff: render */
1487 GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*
1488 0xe900 - 0xe9ff: gt
1489 0xea00 - 0xefff: reserved
1490 0xf000 - 0xffff: gt */
1491 GEN_FW_RANGE(0x10000, 0x12fff, 0), /*
1492 0x10000 - 0x11fff: reserved
1493 0x12000 - 0x127ff: always on
1494 0x12800 - 0x12fff: reserved */
1495 GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0),
1496 GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /*
1497 0x13200 - 0x133ff: VD2 (DG2 only)
1498 0x13400 - 0x147ff: reserved */
1499 GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),
1500 GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
1501 0x15000 - 0x15fff: gt (DG2 only)
1502 0x16000 - 0x16dff: reserved */
1503 GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /*
1504 0x16e00 - 0x1ffff: render
1505 0x20000 - 0x21fff: reserved */
1506 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1507 GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1508 0x24000 - 0x2407f: always on
1509 0x24080 - 0x2417f: reserved */
1510 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
1511 0x24180 - 0x241ff: gt
1512 0x24200 - 0x249ff: reserved */
1513 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
1514 0x24a00 - 0x24a7f: render
1515 0x24a80 - 0x251ff: reserved */
1516 GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*
1517 0x25200 - 0x252ff: gt
1518 0x25300 - 0x25fff: reserved */
1519 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
1520 0x26000 - 0x27fff: render
1521 0x28000 - 0x29fff: reserved
1522 0x2a000 - 0x2ffff: undocumented */
1523 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1524 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1525 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1526 0x1c0000 - 0x1c2bff: VD0
1527 0x1c2c00 - 0x1c2cff: reserved
1528 0x1c2d00 - 0x1c2dff: VD0
1529 0x1c2e00 - 0x1c3eff: VD0
1530 0x1c3f00 - 0x1c3fff: VD0 */
1531 GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*
1532 0x1c4000 - 0x1c6bff: VD1
1533 0x1c6c00 - 0x1c6cff: reserved
1534 0x1c6d00 - 0x1c6dff: VD1
1535 0x1c6e00 - 0x1c7fff: reserved */
1536 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1537 0x1c8000 - 0x1ca0ff: VE0
1538 0x1ca100 - 0x1cbfff: reserved */
1539 GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0),
1540 GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2),
1541 GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4),
1542 GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6),
1543 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
1544 0x1d0000 - 0x1d2bff: VD2
1545 0x1d2c00 - 0x1d2cff: reserved
1546 0x1d2d00 - 0x1d2dff: VD2
1547 0x1d2e00 - 0x1d3dff: VD2
1548 0x1d3e00 - 0x1d3eff: reserved
1549 0x1d3f00 - 0x1d3fff: VD2 */
1550 GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*
1551 0x1d4000 - 0x1d6bff: VD3
1552 0x1d6c00 - 0x1d6cff: reserved
1553 0x1d6d00 - 0x1d6dff: VD3
1554 0x1d6e00 - 0x1d7fff: reserved */
1555 GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*
1556 0x1d8000 - 0x1da0ff: VE1
1557 0x1da100 - 0x1dffff: reserved */
1558 GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*
1559 0x1e0000 - 0x1e2bff: VD4
1560 0x1e2c00 - 0x1e2cff: reserved
1561 0x1e2d00 - 0x1e2dff: VD4
1562 0x1e2e00 - 0x1e3eff: reserved
1563 0x1e3f00 - 0x1e3fff: VD4 */
1564 GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*
1565 0x1e4000 - 0x1e6bff: VD5
1566 0x1e6c00 - 0x1e6cff: reserved
1567 0x1e6d00 - 0x1e6dff: VD5
1568 0x1e6e00 - 0x1e7fff: reserved */
1569 GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*
1570 0x1e8000 - 0x1ea0ff: VE2
1571 0x1ea100 - 0x1effff: reserved */
1572 GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*
1573 0x1f0000 - 0x1f2bff: VD6
1574 0x1f2c00 - 0x1f2cff: reserved
1575 0x1f2d00 - 0x1f2dff: VD6
1576 0x1f2e00 - 0x1f3eff: reserved
1577 0x1f3f00 - 0x1f3fff: VD6 */
1578 GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*
1579 0x1f4000 - 0x1f6bff: VD7
1580 0x1f6c00 - 0x1f6cff: reserved
1581 0x1f6d00 - 0x1f6dff: VD7
1582 0x1f6e00 - 0x1f7fff: reserved */
1583 GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
1587 GEN_FW_RANGE(0x0, 0xaff, 0),
1588 GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
1589 GEN_FW_RANGE(0xc00, 0xfff, 0),
1590 GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
1591 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1592 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1593 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1594 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
1595 0x4000 - 0x48ff: render
1596 0x4900 - 0x51ff: reserved */
1597 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
1598 0x5200 - 0x53ff: render
1599 0x5400 - 0x54ff: reserved
1600 0x5500 - 0x7fff: render */
1601 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1602 GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER), /*
1603 0x8140 - 0x815f: render
1604 0x8160 - 0x817f: reserved */
1605 GEN_FW_RANGE(0x8180, 0x81ff, 0),
1606 GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
1607 0x8200 - 0x87ff: gt
1608 0x8800 - 0x8dff: reserved
1609 0x8e00 - 0x8f7f: gt
1610 0x8f80 - 0x8fff: reserved
1611 0x9000 - 0x947f: gt
1612 0x9480 - 0x94cf: reserved */
1613 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1614 GEN_FW_RANGE(0x9560, 0x967f, 0), /*
1615 0x9560 - 0x95ff: always on
1616 0x9600 - 0x967f: reserved */
1617 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
1618 0x9680 - 0x96ff: render
1619 0x9700 - 0x97ff: reserved */
1620 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
1621 0x9800 - 0xb4ff: gt
1622 0xb500 - 0xbfff: reserved
1623 0xc000 - 0xcfff: gt */
1624 GEN_FW_RANGE(0xd000, 0xd7ff, 0), /*
1625 0xd000 - 0xd3ff: always on
1626 0xd400 - 0xd7ff: reserved */
1627 GEN_FW_RANGE(0xd800, 0xd87f, FORCEWAKE_RENDER),
1628 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT),
1629 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
1630 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
1631 0xdd00 - 0xddff: gt
1632 0xde00 - 0xde7f: reserved */
1633 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
1634 0xde80 - 0xdfff: render
1635 0xe000 - 0xe0ff: reserved
1636 0xe100 - 0xe8ff: render */
1637 GEN_FW_RANGE(0xe900, 0xe9ff, FORCEWAKE_GT),
1638 GEN_FW_RANGE(0xea00, 0x147ff, 0), /*
1639 0xea00 - 0x11fff: reserved
1640 0x12000 - 0x127ff: always on
1641 0x12800 - 0x147ff: reserved */
1642 GEN_FW_RANGE(0x14800, 0x19fff, FORCEWAKE_GT), /*
1643 0x14800 - 0x153ff: gt
1644 0x15400 - 0x19fff: reserved */
1645 GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
1646 0x1a000 - 0x1bfff: render
1647 0x1c000 - 0x21fff: reserved */
1648 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1649 GEN_FW_RANGE(0x24000, 0x2ffff, 0), /*
1650 0x24000 - 0x2407f: always on
1651 0x24080 - 0x2ffff: reserved */
1652 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1653 GEN_FW_RANGE(0x40000, 0x1901ef, 0),
1654 GEN_FW_RANGE(0x1901f0, 0x1901f3, FORCEWAKE_GT)
1660 * translation of the GSI block to the 0x380000 offset.
1673 GEN_FW_RANGE(0x0, 0x115fff, 0), /* render GT range */
1674 GEN_FW_RANGE(0x116000, 0x11ffff, FORCEWAKE_GSC), /*
1675 0x116000 - 0x117fff: gsc
1676 0x118000 - 0x119fff: reserved
1677 0x11a000 - 0x11efff: gsc
1678 0x11f000 - 0x11ffff: reserved */
1679 GEN_FW_RANGE(0x120000, 0x1bffff, 0), /* non-GT range */
1680 GEN_FW_RANGE(0x1c0000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX0), /*
1681 0x1c0000 - 0x1c3dff: VD0
1682 0x1c3e00 - 0x1c3eff: reserved
1683 0x1c3f00 - 0x1c3fff: VD0
1684 0x1c4000 - 0x1c7fff: reserved */
1685 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1686 0x1c8000 - 0x1ca0ff: VE0
1687 0x1ca100 - 0x1cbfff: reserved */
1688 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
1689 0x1cc000 - 0x1cdfff: VD0
1690 0x1ce000 - 0x1cffff: reserved */
1691 GEN_FW_RANGE(0x1d0000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX2), /*
1692 0x1d0000 - 0x1d3dff: VD2
1693 0x1d3e00 - 0x1d3eff: reserved
1694 0x1d4000 - 0x1d7fff: VD2 */
1695 GEN_FW_RANGE(0x1d8000, 0x1da0ff, FORCEWAKE_MEDIA_VEBOX1),
1696 GEN_FW_RANGE(0x1da100, 0x380aff, 0), /*
1697 0x1da100 - 0x23ffff: reserved
1698 0x240000 - 0x37ffff: non-GT range
1699 0x380000 - 0x380aff: reserved */
1700 GEN_FW_RANGE(0x380b00, 0x380bff, FORCEWAKE_GT),
1701 GEN_FW_RANGE(0x380c00, 0x380fff, 0),
1702 GEN_FW_RANGE(0x381000, 0x38817f, FORCEWAKE_GT), /*
1703 0x381000 - 0x381fff: gt
1704 0x382000 - 0x383fff: reserved
1705 0x384000 - 0x384aff: gt
1706 0x384b00 - 0x3851ff: reserved
1707 0x385200 - 0x3871ff: gt
1708 0x387200 - 0x387fff: reserved
1709 0x388000 - 0x38813f: gt
1710 0x388140 - 0x38817f: reserved */
1711 GEN_FW_RANGE(0x388180, 0x3882ff, 0), /*
1712 0x388180 - 0x3881ff: always on
1713 0x388200 - 0x3882ff: reserved */
1714 GEN_FW_RANGE(0x388300, 0x38955f, FORCEWAKE_GT), /*
1715 0x388300 - 0x38887f: gt
1716 0x388880 - 0x388fff: reserved
1717 0x389000 - 0x38947f: gt
1718 0x389480 - 0x38955f: reserved */
1719 GEN_FW_RANGE(0x389560, 0x389fff, 0), /*
1720 0x389560 - 0x3895ff: always on
1721 0x389600 - 0x389fff: reserved */
1722 GEN_FW_RANGE(0x38a000, 0x38cfff, FORCEWAKE_GT), /*
1723 0x38a000 - 0x38afff: gt
1724 0x38b000 - 0x38bfff: reserved
1725 0x38c000 - 0x38cfff: gt */
1726 GEN_FW_RANGE(0x38d000, 0x38d11f, 0),
1727 GEN_FW_RANGE(0x38d120, 0x391fff, FORCEWAKE_GT), /*
1728 0x38d120 - 0x38dfff: gt
1729 0x38e000 - 0x38efff: reserved
1730 0x38f000 - 0x38ffff: gt
1731 0x389000 - 0x391fff: reserved */
1732 GEN_FW_RANGE(0x392000, 0x392fff, 0), /*
1733 0x392000 - 0x3927ff: always on
1734 0x392800 - 0x292fff: reserved */
1735 GEN_FW_RANGE(0x393000, 0x3931ff, FORCEWAKE_GT),
1736 GEN_FW_RANGE(0x393200, 0x39323f, FORCEWAKE_ALL), /* instance-based, see note above */
1737 GEN_FW_RANGE(0x393240, 0x3933ff, FORCEWAKE_GT),
1738 GEN_FW_RANGE(0x393400, 0x3934ff, FORCEWAKE_ALL), /* instance-based, see note above */
1739 GEN_FW_RANGE(0x393500, 0x393c7f, 0), /*
1740 0x393500 - 0x393bff: reserved
1741 0x393c00 - 0x393c7f: always on */
1742 GEN_FW_RANGE(0x393c80, 0x393dff, FORCEWAKE_GT),
1750 * hence harmless to write 0 into. */ in ilk_dummy_write()
1751 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); in ilk_dummy_write()
1761 "Unclaimed %s register 0x%x\n", in __unclaimed_reg_debug()
1775 "Unclaimed access detected before %s register 0x%x\n", in __unclaimed_previous_reg_debug()
1820 u##x val = 0; \
1863 u##x val = 0; \
2033 } while (0)
2041 } while (0)
2047 } while (0)
2053 } while (0)
2076 d->wake_count = 0; in __fw_domain_init()
2110 return 0; in __fw_domain_init()
2154 int ret = 0; in intel_uncore_fw_domains_init()
2183 for (i = 0; i < I915_MAX_VCS; i++) { in intel_uncore_fw_domains_init()
2191 for (i = 0; i < I915_MAX_VECS; i++) { in intel_uncore_fw_domains_init()
2244 __raw_uncore_write32(uncore, FORCEWAKE, 0); in intel_uncore_fw_domains_init()
2274 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0); in intel_uncore_fw_domains_init()
2404 return 0; in uncore_media_forcewake_init()
2417 forcewake_early_sanitize(uncore, 0); in uncore_forcewake_init()
2463 return 0; in uncore_forcewake_init()
2471 return 0; in sanity_check_mmio_access()
2476 * return 0xFFFFFFFF. Let's make sure the device isn't in this state in sanity_check_mmio_access()
2487 #define COND (__raw_uncore_read32(uncore, FORCEWAKE_MT) != ~0) in sanity_check_mmio_access()
2489 drm_err(&i915->drm, "Device is non-operational; MMIO access returns 0xFFFFFFFF!\n"); in sanity_check_mmio_access()
2493 return 0; in sanity_check_mmio_access()
2546 return 0; in intel_uncore_init_mmio()
2564 for (i = 0; i < I915_MAX_VCS; i++) { in intel_uncore_prune_engine_fw_domains()
2578 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 55) && i % 2 == 0) { in intel_uncore_prune_engine_fw_domains()
2590 for (i = 0; i < I915_MAX_VECS; i++) { in intel_uncore_prune_engine_fw_domains()
2641 ret = intel_wait_for_register_fw(uncore, GU_CNTL, DRIVERFLR, 0, flr_timeout_ms); in driver_initiated_flr()
2651 intel_uncore_rmw_fw(uncore, GU_CNTL, 0, DRIVERFLR); in driver_initiated_flr()
2655 DRIVERFLR, 0, in driver_initiated_flr()
2717 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2727 u32 reg_value = 0; in __intel_wait_for_register_fw()
2738 ret = _wait_for_atomic(done, fast_timeout_us, 0); in __intel_wait_for_register_fw()
2766 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2788 fast_timeout_us, 0, ®_value); in __intel_wait_for_register()
2832 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) in intel_uncore_arm_unclaimed_mmio_detection()
2871 enum forcewake_domains fw_domains = 0; in intel_uncore_forcewake_for_reg()
2876 return 0; in intel_uncore_forcewake_for_reg()