Lines Matching +full:1 +full:- +full:based

1 /* SPDX-License-Identifier: MIT */
13 * REG_BIT() - Prepare a u32 bit value
14 * @__n: 0-based bit number
26 * REG_BIT8() - Prepare a u8 bit value
27 * @__n: 0-based bit number
39 * REG_GENMASK() - Prepare a continuous u32 bitmask
40 * @__high: 0-based high bit
41 * @__low: 0-based low bit
54 * REG_GENMASK64() - Prepare a continuous u64 bitmask
55 * @__high: 0-based high bit
56 * @__low: 0-based low bit
69 * REG_GENMASK8() - Prepare a continuous u8 bitmask
70 * @__high: 0-based high bit
71 * @__low: 0-based low bit
86 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
89 * REG_FIELD_PREP() - Prepare a u32 bitfield value
102 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
106 * REG_FIELD_PREP8() - Prepare a u8 bitfield value
119 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
123 * REG_FIELD_GET() - Extract a u32 bitfield value
135 * REG_FIELD_GET64() - Extract a u64 bitfield value
147 * REG_BIT16() - Prepare a u16 bit value
148 * @__n: 0-based bit number
161 * REG_GENMASK16() - Prepare a continuous u8 bitmask
162 * @__high: 0-based high bit
163 * @__low: 0-based low bit
177 * REG_FIELD_PREP16() - Prepare a u16 bitfield value
191 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
209 * numbers, pick the 0-based __index'th value.
213 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
232 * 1: 0xf004,
242 _PICK_EVEN((__index) - (__c_index), __c, __d)))
245 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
252 * REG_FIELD_GET8() - Extract a u8 bitfield value
280 * non-MCR nature of the register.