Lines Matching refs:_MMIO
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
147 #define _VGA_MSR_WRITE _MMIO(0x3c2)
156 #define DEBUG_RESET_I830 _MMIO(0x6070)
164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
198 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
215 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
220 #define UAIMI_SPR1 _MMIO(0x4F074)
224 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
242 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
255 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
256 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
262 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
263 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
269 #define TILECTL _MMIO(0x101000)
278 #define PGTBL_CTL _MMIO(0x02020)
281 #define PGTBL_ER _MMIO(0x02024)
327 #define HECI_H_CSR(base) _MMIO((base) + 0x4)
334 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
354 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
362 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
364 #define GEN7_WR_WATERMARK _MMIO(0x4028)
365 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
366 #define ARB_MODE _MMIO(0x4030)
369 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
370 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
372 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
374 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
375 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
377 #define GEN7_ERR_INT _MMIO(0x44040)
389 #define FPGA_DBG _MMIO(0x42300)
392 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
397 #define DERRMR _MMIO(0x44050)
416 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
417 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
418 #define SCPD0 _MMIO(0x209c) /* 915+ only */
421 #define GEN2_IER _MMIO(0x20a0)
422 #define GEN2_IIR _MMIO(0x20a4)
423 #define GEN2_IMR _MMIO(0x20a8)
424 #define GEN2_ISR _MMIO(0x20ac)
425 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
428 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
429 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
430 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
431 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
432 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
433 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
434 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
438 #define EIR _MMIO(0x20b0)
439 #define EMR _MMIO(0x20b4)
440 #define ESR _MMIO(0x20b8)
447 #define INSTPM _MMIO(0x20c0)
455 #define MEM_MODE _MMIO(0x20cc)
459 #define FW_BLC _MMIO(0x20d8)
460 #define FW_BLC2 _MMIO(0x20dc)
461 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
469 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
475 _MMIO(_PICK_EVEN_2RANGES(x, 2, \
550 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
626 #define GEN6_BSD_RNCID _MMIO(0x12198)
628 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
646 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
661 #define IPS_CTL _MMIO(0x43408)
674 #define VGA0 _MMIO(0x6000)
675 #define VGA1 _MMIO(0x6004)
676 #define VGA_PD _MMIO(0x6010)
712 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
714 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
725 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
811 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
827 #define DPLL_TEST _MMIO(0x606c)
838 #define D_STATE _MMIO(0x6104)
843 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
883 #define RENCLK_GATE_D1 _MMIO(0x6204)
947 #define RENCLK_GATE_D2 _MMIO(0x6208)
952 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
955 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
956 #define DEUC _MMIO(0x6214) /* CRL only */
958 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
961 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
963 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
968 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
975 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
977 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
979 #define BXT_RP_STATE_CAP _MMIO(0x138170)
980 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
982 #define MTL_RP_STATE_CAP _MMIO(0x138000)
983 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
987 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
988 #define MTL_MPE_FREQUENCY _MMIO(0x13802c)
991 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1002 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1004 #define CHV_CLK_CTL1 _MMIO(0x101100)
1005 #define VLV_CLK_CTL2 _MMIO(0x101104)
1012 #define OVADD _MMIO(0x30000)
1013 #define DOVSTA _MMIO(0x30008)
1015 #define OGAMC5 _MMIO(0x30010)
1016 #define OGAMC4 _MMIO(0x30014)
1017 #define OGAMC3 _MMIO(0x30018)
1018 #define OGAMC2 _MMIO(0x3001c)
1019 #define OGAMC1 _MMIO(0x30020)
1020 #define OGAMC0 _MMIO(0x30024)
1025 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1032 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1036 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1039 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1151 #define ADPA _MMIO(0x61100)
1152 #define PCH_ADPA _MMIO(0xe1100)
1153 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
1200 #define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
1230 #define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
1287 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
1288 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
1291 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
1292 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
1293 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
1294 #define PCH_SDVOB _MMIO(0xe1140)
1296 #define PCH_HDMIC _MMIO(0xe1150)
1297 #define PCH_HDMID _MMIO(0xe1160)
1299 #define PORT_DFT_I9XX _MMIO(0x61150)
1301 #define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
1362 #define VIDEO_DIP_DATA _MMIO(0x61178)
1371 #define VIDEO_DIP_CTL _MMIO(0x61170)
1410 #define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
1431 #define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
1439 #define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
1441 #define PCH_GTC_CTL _MMIO(0xe7000)
1445 #define DP_A _MMIO(0x64000) /* eDP */
1446 #define DP_B _MMIO(0x64100)
1447 #define DP_C _MMIO(0x64200)
1448 #define DP_D _MMIO(0x64300)
1450 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
1451 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
1452 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
1755 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
1776 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
1806 #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
1821 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
1834 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
1841 #define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
1852 #define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
1868 #define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
1879 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
1886 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
1895 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
1898 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
1899 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
1908 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
1917 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
1928 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
1949 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
1972 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
1980 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
1984 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
2032 #define WM1_LP_ILK _MMIO(0x45108)
2033 #define WM2_LP_ILK _MMIO(0x4510c)
2034 #define WM3_LP_ILK _MMIO(0x45110)
2046 #define WM1S_LP_ILK _MMIO(0x45120)
2047 #define WM2S_LP_IVB _MMIO(0x45124)
2048 #define WM3S_LP_IVB _MMIO(0x45128)
2112 #define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
2113 #define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
2114 #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
2115 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
2123 #define VGACNTRL _MMIO(0x71400)
2128 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
2132 #define CPU_VGACNTRL _MMIO(0x41000)
2134 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
2147 #define RR_HW_CTL _MMIO(0x45300)
2151 #define PCH_3DCGDIS0 _MMIO(0x46020)
2155 #define PCH_3DCGDIS1 _MMIO(0x46024)
2398 #define RM_TIMEOUT _MMIO(0x42060)
2399 #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
2454 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
2457 #define DEISR _MMIO(0x44000)
2458 #define DEIMR _MMIO(0x44004)
2459 #define DEIIR _MMIO(0x44008)
2460 #define DEIER _MMIO(0x4400c)
2462 #define GTISR _MMIO(0x44010)
2463 #define GTIMR _MMIO(0x44014)
2464 #define GTIIR _MMIO(0x44018)
2465 #define GTIER _MMIO(0x4401c)
2467 #define GEN8_MASTER_IRQ _MMIO(0x44200)
2485 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
2487 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
2488 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
2489 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
2490 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
2499 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
2500 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
2501 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
2502 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
2546 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
2547 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
2548 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
2549 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
2578 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
2579 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
2580 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
2581 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
2588 #define GEN8_PCU_ISR _MMIO(0x444e0)
2589 #define GEN8_PCU_IMR _MMIO(0x444e4)
2590 #define GEN8_PCU_IIR _MMIO(0x444e8)
2591 #define GEN8_PCU_IER _MMIO(0x444ec)
2593 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
2594 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
2595 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
2596 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
2599 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
2608 #define DG1_MSTR_TILE_INTR _MMIO(0x190008)
2612 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
2623 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
2624 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
2625 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
2626 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
2642 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
2643 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
2649 #define PICAINTERRUPT_ISR _MMIO(0x16FE50)
2650 #define PICAINTERRUPT_IMR _MMIO(0x16FE54)
2651 #define PICAINTERRUPT_IIR _MMIO(0x16FE58)
2652 #define PICAINTERRUPT_IER _MMIO(0x16FE5C)
2662 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
2670 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
2684 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
2687 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
2693 #define FUSE_STRAP _MMIO(0x42014)
2704 #define FUSE_STRAP3 _MMIO(0x42020)
2707 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
2714 #define IVB_CHICKEN3 _MMIO(0x4200c)
2718 #define CHICKEN_PAR1_1 _MMIO(0x42080)
2728 #define CHICKEN_PAR2_1 _MMIO(0x42090)
2731 #define CHICKEN_MISC_2 _MMIO(0x42084)
2740 #define CHICKEN_MISC_3 _MMIO(0x42088)
2745 #define CHICKEN_MISC_4 _MMIO(0x4208c)
2778 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
2806 #define DISP_ARB_CTL _MMIO(0x45000)
2811 #define DISP_ARB_CTL2 _MMIO(0x45004)
2815 #define GEN7_MSG_CTL _MMIO(0x45010)
2821 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
2830 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
2834 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
2838 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
2849 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
2855 #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
2858 #define SKL_DFSM _MMIO(0x51000)
2873 #define XE2LPD_DE_CAP _MMIO(0x41100)
2880 #define SKL_DSSM _MMIO(0x51004)
2886 #define GMD_ID_DISPLAY _MMIO(0x510a0)
3013 #define SDEISR _MMIO(0xc4000)
3014 #define SDEIMR _MMIO(0xc4004)
3015 #define SDEIIR _MMIO(0xc4008)
3016 #define SDEIER _MMIO(0xc400c)
3018 #define SERR_INT _MMIO(0xc4040)
3023 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
3066 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
3078 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
3087 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
3092 #define SHPD_FILTER_CNT _MMIO(0xc4038)
3098 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3105 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
3106 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
3108 #define PCH_DPLL_TEST _MMIO(0xc606c)
3110 #define PCH_DREF_CONTROL _MMIO(0xC6200)
3133 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
3145 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
3147 #define PCH_SSC4_PARMS _MMIO(0xc6210)
3148 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
3150 #define PCH_DPLL_SEL _MMIO(0xc7000)
3358 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
3379 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
3385 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
3394 #define PCH_DP_B _MMIO(0xe4100)
3395 #define PCH_DP_C _MMIO(0xe4200)
3396 #define PCH_DP_D _MMIO(0xe4300)
3472 #define VLV_PMWGICZ _MMIO(0x1300a4)
3474 #define HSW_EDRAM_CAP _MMIO(0x120010)
3480 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
3484 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
3583 #define GEN6_PCODE_DATA _MMIO(0x138128)
3586 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
3588 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
3592 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
3609 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
3626 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
3627 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
3628 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
3629 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
3662 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
3663 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
3664 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
3690 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
3691 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
3692 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
3709 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
3713 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
3724 #define SKL_FUSE_STATUS _MMIO(0x42000)
3809 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
3880 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
3882 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 +…
3900 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) *…
3905 #define SBI_ADDR _MMIO(0xC6000)
3906 #define SBI_DATA _MMIO(0xC6004)
3907 #define SBI_CTL_STAT _MMIO(0xC6008)
3944 #define PIXCLK_GATE _MMIO(0xC6020)
3949 #define SPLL_CTL _MMIO(0x46020)
4018 #define CDCLK_FREQ _MMIO(0x46200)
4036 #define LCPLL_CTL _MMIO(0x130040)
4060 #define CDCLK_CTL _MMIO(0x46000)
4085 #define CDCLK_SQUASH_CTL _MMIO(0x46008)
4093 #define LCPLL1_CTL _MMIO(0x46010)
4094 #define LCPLL2_CTL _MMIO(0x46014)
4098 #define DPLL_CTRL1 _MMIO(0x6C058)
4113 #define DPLL_CTRL2 _MMIO(0x6C05C)
4121 #define DPLL_STATUS _MMIO(0x6C060)
4158 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
4221 #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
4227 #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
4231 #define TBT_PLL_ENABLE _MMIO(0x46020)
4242 #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4304 #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4319 #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4327 #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4333 #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4340 #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4346 #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4351 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
4355 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
4364 #define DC_STATE_EN _MMIO(0x45504)
4375 #define DC_STATE_DEBUG _MMIO(0x45520)
4379 #define D_COMP_BDW _MMIO(0x138144)
4391 #define SFUSE_STRAP _MMIO(0xc2014)
4401 #define WM_MISC _MMIO(0x45260)
4404 #define WM_DBG _MMIO(0x45280)
4410 #define GEN4_TIMESTAMP _MMIO(0x2358)
4411 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
4412 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
4414 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
4444 #define GGC _MMIO(0x108040)
4448 #define GEN6_GSMBASE _MMIO(0x108100)
4449 #define GEN6_DSMBASE _MMIO(0x1080C0)
4453 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
4462 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
4489 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
4497 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
4498 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
4499 #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
4500 #define SPI_STATIC_REGIONS _MMIO(0x102090)
4502 #define OROM_OFFSET _MMIO(0x1020c0)
4505 #define CLKREQ_POLICY _MMIO(0x101038)
4508 #define CLKGATE_DIS_MISC _MMIO(0x46534)
4516 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
4522 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
4527 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 …