Lines Matching refs:REG_GENMASK
342 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
395 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
650 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
655 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
984 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
985 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
989 #define MTL_RPE_MASK REG_GENMASK(8, 0)
1001 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
1074 #define HTOTAL_MASK REG_GENMASK(31, 16)
1076 #define HACTIVE_MASK REG_GENMASK(15, 0)
1079 #define HBLANK_END_MASK REG_GENMASK(31, 16)
1081 #define HBLANK_START_MASK REG_GENMASK(15, 0)
1084 #define HSYNC_END_MASK REG_GENMASK(31, 16)
1086 #define HSYNC_START_MASK REG_GENMASK(15, 0)
1089 #define VTOTAL_MASK REG_GENMASK(31, 16)
1091 #define VACTIVE_MASK REG_GENMASK(15, 0)
1094 #define VBLANK_END_MASK REG_GENMASK(31, 16)
1096 #define VBLANK_START_MASK REG_GENMASK(15, 0)
1099 #define VSYNC_END_MASK REG_GENMASK(31, 16)
1101 #define VSYNC_START_MASK REG_GENMASK(15, 0)
1105 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
1107 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1412 #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
1414 #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
1419 #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
1423 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
1426 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
1432 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
1434 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
1436 #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
1437 #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
1554 #define TU_SIZE_MASK REG_GENMASK(30, 25)
1557 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
1587 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
1593 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
1598 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
1604 #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
1614 #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
1615 #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
1622 #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
1628 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
1633 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
1639 #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
1644 #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
1726 #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
1732 #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
1741 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
1744 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1777 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
1778 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
1791 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
1792 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
2026 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
2027 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
2028 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
2036 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
2037 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
2038 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
2039 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
2040 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
2050 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
2084 #define CHV_BLEND_MASK REG_GENMASK(31, 30)
2089 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
2090 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
2091 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
2192 #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
2194 #define PF_FILTER_MASK REG_GENMASK(24, 23)
2201 #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
2203 #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2207 #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
2209 #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
2234 #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
2242 #define PS_BINDING_MASK REG_GENMASK(27, 25)
2245 #define PS_FILTER_MASK REG_GENMASK(24, 23)
2262 #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
2266 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
2283 #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
2288 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
2299 #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
2301 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
2309 #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
2311 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2331 #define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
2333 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
2654 #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
2656 #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
2658 #define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
2660 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
2671 #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
2672 #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
2673 #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
2674 #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
2675 #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
2676 #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
2679 #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
2680 #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
2681 #define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
2682 #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
2747 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
2753 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
2758 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
2766 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
2791 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
2825 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
2874 #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
2875 #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
2877 #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
2887 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
2888 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
2889 #define GMD_ID_STEP REG_GENMASK(5, 0)
3330 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
3332 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
3336 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
3353 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
3404 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
3409 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
3431 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
3486 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
3487 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
3488 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
3507 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
3508 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
3509 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
3510 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
3523 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
3527 #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
3528 #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
3537 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
3541 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
3545 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
3547 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
3573 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
3769 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
3781 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
3791 #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
3806 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
3864 #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
3987 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
3999 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
4032 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
4061 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
4066 #define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
4069 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
4087 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
4089 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
4199 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
4200 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
4201 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
4203 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
4204 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
4313 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
4385 #define HSW_LINETIME_MASK REG_GENMASK(8, 0)
4387 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
4442 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
4445 #define GMS_MASK REG_GENMASK(15, 8)
4446 #define GGMS_MASK REG_GENMASK(7, 6)
4466 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
4492 #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
4501 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
4503 #define OROM_OFFSET_MASK REG_GENMASK(20, 16)
4517 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
4518 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
4519 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
4523 #define MTL_TRCD_MASK REG_GENMASK(31, 24)
4524 #define MTL_TRP_MASK REG_GENMASK(23, 16)
4525 #define MTL_DCLK_MASK REG_GENMASK(15, 0)
4528 #define MTL_TRAS_MASK REG_GENMASK(16, 8)
4529 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)