Lines Matching +full:0 +full:xc4000
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
132 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
137 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
140 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
147 #define _VGA_MSR_WRITE _MMIO(0x3c2)
149 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
150 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
156 #define DEBUG_RESET_I830 _MMIO(0x6070)
164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
170 #define IOSF_SB_BUSY (1 << 0)
171 #define IOSF_PORT_BUNIT 0x03
172 #define IOSF_PORT_PUNIT 0x04
173 #define IOSF_PORT_NC 0x11
174 #define IOSF_PORT_DPIO 0x12
175 #define IOSF_PORT_GPIO_NC 0x13
176 #define IOSF_PORT_CCK 0x14
177 #define IOSF_PORT_DPIO_2 0x1a
178 #define IOSF_PORT_FLISDSI 0x1b
179 #define IOSF_PORT_GPIO_SC 0x48
180 #define IOSF_PORT_GPIO_SUS 0xa8
181 #define IOSF_PORT_CCU 0xa9
182 #define CHV_IOSF_PORT_GPIO_N 0x13
183 #define CHV_IOSF_PORT_GPIO_SE 0x48
184 #define CHV_IOSF_PORT_GPIO_E 0xa8
185 #define CHV_IOSF_PORT_GPIO_SW 0xb2
186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
190 #define DPIO_DEVFN 0
192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
196 #define DPIO_CMNRST (1 << 0)
198 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
201 #define _BXT_PHY_CTL_DDI_A 0x64C00
202 #define _BXT_PHY_CTL_DDI_B 0x64C10
203 #define _BXT_PHY_CTL_DDI_C 0x64C20
210 #define _PHY_CTL_FAMILY_DDI 0x64C90
211 #define _PHY_CTL_FAMILY_EDP 0x64C80
212 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
220 #define UAIMI_SPR1 _MMIO(0x4F074)
222 #define SKL_VCCIO_MASK 0x1
224 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
234 * [0-7] @ 0x2000 gen2,gen3
235 * [8-15] @ 0x3000 945,g33,pnv
237 * [0-15] @ 0x3000 gen4,gen5
239 * [0-15] @ 0x100000 gen6,vlv,chv
240 * [0-31] @ 0x100000 gen7+
242 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
243 #define I830_FENCE_START_MASK 0x07f80000
247 #define I830_FENCE_REG_VALID (1 << 0)
252 #define I915_FENCE_START_MASK 0x0ff00000
255 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
256 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
259 #define I965_FENCE_REG_VALID (1 << 0)
260 #define I965_FENCE_MAX_PITCH_VAL 0x0400
262 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
263 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
265 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
269 #define TILECTL _MMIO(0x101000)
270 #define TILECTL_SWZCTL (1 << 0)
278 #define PGTBL_CTL _MMIO(0x02020)
279 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
280 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
281 #define PGTBL_ER _MMIO(0x02024)
282 #define PRB0_BASE (0x2030 - 0x30)
283 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
284 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
285 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
286 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
287 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
288 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
289 #define RENDER_RING_BASE 0x02000
290 #define BSD_RING_BASE 0x04000
291 #define GEN6_BSD_RING_BASE 0x12000
292 #define GEN8_BSD2_RING_BASE 0x1c000
293 #define GEN11_BSD_RING_BASE 0x1c0000
294 #define GEN11_BSD2_RING_BASE 0x1c4000
295 #define GEN11_BSD3_RING_BASE 0x1d0000
296 #define GEN11_BSD4_RING_BASE 0x1d4000
297 #define XEHP_BSD5_RING_BASE 0x1e0000
298 #define XEHP_BSD6_RING_BASE 0x1e4000
299 #define XEHP_BSD7_RING_BASE 0x1f0000
300 #define XEHP_BSD8_RING_BASE 0x1f4000
301 #define VEBOX_RING_BASE 0x1a000
302 #define GEN11_VEBOX_RING_BASE 0x1c8000
303 #define GEN11_VEBOX2_RING_BASE 0x1d8000
304 #define XEHP_VEBOX3_RING_BASE 0x1e8000
305 #define XEHP_VEBOX4_RING_BASE 0x1f8000
306 #define MTL_GSC_RING_BASE 0x11a000
307 #define GEN12_COMPUTE0_RING_BASE 0x1a000
308 #define GEN12_COMPUTE1_RING_BASE 0x1c000
309 #define GEN12_COMPUTE2_RING_BASE 0x1e000
310 #define GEN12_COMPUTE3_RING_BASE 0x26000
311 #define BLT_RING_BASE 0x22000
312 #define XEHPC_BCS1_RING_BASE 0x3e0000
313 #define XEHPC_BCS2_RING_BASE 0x3e2000
314 #define XEHPC_BCS3_RING_BASE 0x3e4000
315 #define XEHPC_BCS4_RING_BASE 0x3e6000
316 #define XEHPC_BCS5_RING_BASE 0x3e8000
317 #define XEHPC_BCS6_RING_BASE 0x3ea000
318 #define XEHPC_BCS7_RING_BASE 0x3ec000
319 #define XEHPC_BCS8_RING_BASE 0x3ee000
320 #define DG1_GSC_HECI1_BASE 0x00258000
321 #define DG1_GSC_HECI2_BASE 0x00259000
322 #define DG2_GSC_HECI1_BASE 0x00373000
323 #define DG2_GSC_HECI2_BASE 0x00374000
324 #define MTL_GSC_HECI1_BASE 0x00116000
325 #define MTL_GSC_HECI2_BASE 0x00117000
327 #define HECI_H_CSR(base) _MMIO((base) + 0x4)
328 #define HECI_H_CSR_IE REG_BIT(0)
334 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
335 #define HECI_H_GS1_ER_PREP REG_BIT(0)
341 #define HECI_FWSTS1 0xc40
342 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
343 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0
346 #define HECI_FWSTS2 0xc48
347 #define HECI_FWSTS3 0xc60
348 #define HECI_FWSTS4 0xc64
349 #define HECI_FWSTS5 0xc68
351 #define HECI_FWSTS6 0xc6c
353 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
362 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
363 #define GTT_CACHE_EN_ALL 0xF0007FFF
364 #define GEN7_WR_WATERMARK _MMIO(0x4028)
365 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
366 #define ARB_MODE _MMIO(0x4030)
369 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
370 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
372 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
374 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
375 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
377 #define GEN7_ERR_INT _MMIO(0x44040)
386 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
389 #define FPGA_DBG _MMIO(0x42300)
392 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
395 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
397 #define DERRMR _MMIO(0x44050)
399 #define DERRMR_PIPEA_SCANLINE (1 << 0)
416 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
417 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
418 #define SCPD0 _MMIO(0x209c) /* 915+ only */
421 #define GEN2_IER _MMIO(0x20a0)
422 #define GEN2_IIR _MMIO(0x20a4)
423 #define GEN2_IMR _MMIO(0x20a8)
424 #define GEN2_ISR _MMIO(0x20ac)
425 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
428 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
429 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
430 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
431 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
432 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
433 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
434 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
438 #define EIR _MMIO(0x20b0)
439 #define EMR _MMIO(0x20b4)
440 #define ESR _MMIO(0x20b8)
446 #define I915_ERROR_INSTRUCTION (1 << 0)
447 #define INSTPM _MMIO(0x20c0)
455 #define MEM_MODE _MMIO(0x20cc)
459 #define FW_BLC _MMIO(0x20d8)
460 #define FW_BLC2 _MMIO(0x20dc)
461 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
465 #define MM_BURST_LENGTH 0x00700000
466 #define MM_FIFO_WATERMARK 0x0001F000
467 #define LM_BURST_LENGTH 0x00000700
468 #define LM_FIFO_WATERMARK 0x0000001F
469 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
471 #define _MBUS_ABOX0_CTL 0x45038
472 #define _MBUS_ABOX1_CTL 0x45048
473 #define _MBUS_ABOX2_CTL 0x4504C
481 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
483 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
485 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
486 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
503 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
530 #define MI_ARB_TIME_SLICE_1 (0 << 5)
540 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
547 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
548 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
550 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
552 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
578 #define GT_RENDER_USER_INTERRUPT (1 << 0)
585 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
623 #define I915_ASLE_INTERRUPT (1 << 0)
626 #define GEN6_BSD_RNCID _MMIO(0x12198)
628 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
629 #define GEN7_FF_SCHED_MASK 0x0077070
632 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
633 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
634 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
635 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
637 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
638 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
639 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
640 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
641 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
642 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
643 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
644 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
646 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
651 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
656 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
661 #define IPS_CTL _MMIO(0x43408)
668 #define _DPLL_A 0x6014
669 #define _DPLL_B 0x6018
670 #define _CHV_DPLL_C 0x6030
674 #define VGA0 _MMIO(0x6000)
675 #define VGA1 _MMIO(0x6004)
676 #define VGA_PD _MMIO(0x6010)
679 #define VGA0_PD_P1_SHIFT 0
680 #define VGA0_PD_P1_MASK (0x1f << 0)
684 #define VGA1_PD_P1_MASK (0x1f << 8)
695 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
697 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
699 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
700 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
701 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
706 #define DPLL_PORTC_READY_MASK (0xf << 4)
707 #define DPLL_PORTB_READY_MASK (0xf)
709 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
712 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
713 #define DPLL_PORTD_READY_MASK (0xf)
714 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
716 #define PHY_LDO_DELAY_0NS 0x0
717 #define PHY_LDO_DELAY_200NS 0x1
718 #define PHY_LDO_DELAY_600NS 0x2
721 #define PHY_CH_SU_PSR 0x1
722 #define PHY_CH_DEEP_PSR 0x7
725 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
734 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
740 #define PLL_REF_INPUT_DREFCLK (0 << 13)
750 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
751 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
759 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
764 #define SDVO_MULTIPLIER_MASK 0x000000ff
766 #define SDVO_MULTIPLIER_SHIFT_VGA 0
768 #define _DPLL_A_MD 0x601c
769 #define _DPLL_B_MD 0x6020
770 #define _CHV_DPLL_C_MD 0x603c
779 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
782 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
801 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
808 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
809 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
811 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
813 #define _FPA0 0x6040
814 #define _FPA1 0x6044
815 #define _FPB0 0x6048
816 #define _FPB1 0x604c
819 #define FP_N_DIV_MASK 0x003f0000
820 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
822 #define FP_M1_DIV_MASK 0x00003f00
824 #define FP_M2_DIV_MASK 0x0000003f
825 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
826 #define FP_M2_DIV_SHIFT 0
827 #define DPLL_TEST _MMIO(0x606c)
828 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
837 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
838 #define D_STATE _MMIO(0x6104)
842 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
843 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
880 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
881 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
883 #define RENCLK_GATE_D1 _MMIO(0x6204)
899 # define SV_CLOCK_GATE_DISABLE (1 << 0)
916 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
945 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
947 #define RENCLK_GATE_D2 _MMIO(0x6208)
952 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
955 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
956 #define DEUC _MMIO(0x6214) /* CRL only */
958 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
961 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
963 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
965 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
966 #define CZCLK_FREQ_MASK 0xf
968 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
975 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
977 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
979 #define BXT_RP_STATE_CAP _MMIO(0x138170)
980 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
982 #define MTL_RP_STATE_CAP _MMIO(0x138000)
983 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
984 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
987 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
988 #define MTL_MPE_FREQUENCY _MMIO(0x13802c)
989 #define MTL_RPE_MASK REG_GENMASK(8, 0)
991 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
992 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
993 #define PROCHOT_MASK REG_BIT(0)
1002 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1004 #define CHV_CLK_CTL1 _MMIO(0x101100)
1005 #define VLV_CLK_CTL2 _MMIO(0x101104)
1012 #define OVADD _MMIO(0x30000)
1013 #define DOVSTA _MMIO(0x30008)
1014 #define OC_BUF (0x3 << 20)
1015 #define OGAMC5 _MMIO(0x30010)
1016 #define OGAMC4 _MMIO(0x30014)
1017 #define OGAMC3 _MMIO(0x30018)
1018 #define OGAMC2 _MMIO(0x3001c)
1019 #define OGAMC1 _MMIO(0x30020)
1020 #define OGAMC0 _MMIO(0x30024)
1025 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1032 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1036 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1039 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1042 #define _CLKGATE_DIS_PSL_A 0x46520
1043 #define _CLKGATE_DIS_PSL_B 0x46524
1044 #define _CLKGATE_DIS_PSL_C 0x46528
1056 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1057 #define _CLKGATE_DIS_PSL_EXT_B 0x46550
1064 #define _DDI_CLK_VALFREQ_A 0x64030
1065 #define _DDI_CLK_VALFREQ_B 0x64130
1073 #define _TRANS_HTOTAL_A 0x60000
1076 #define HACTIVE_MASK REG_GENMASK(15, 0)
1078 #define _TRANS_HBLANK_A 0x60004
1081 #define HBLANK_START_MASK REG_GENMASK(15, 0)
1083 #define _TRANS_HSYNC_A 0x60008
1086 #define HSYNC_START_MASK REG_GENMASK(15, 0)
1088 #define _TRANS_VTOTAL_A 0x6000c
1091 #define VACTIVE_MASK REG_GENMASK(15, 0)
1093 #define _TRANS_VBLANK_A 0x60010
1096 #define VBLANK_START_MASK REG_GENMASK(15, 0)
1098 #define _TRANS_VSYNC_A 0x60014
1101 #define VSYNC_START_MASK REG_GENMASK(15, 0)
1103 #define _TRANS_EXITLINE_A 0x60018
1104 #define _PIPEASRC 0x6001c
1107 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1109 #define _BCLRPAT_A 0x60020
1110 #define _TRANS_VSYNCSHIFT_A 0x60028
1111 #define _TRANS_MULT_A 0x6002c
1114 #define _TRANS_HTOTAL_B 0x61000
1115 #define _TRANS_HBLANK_B 0x61004
1116 #define _TRANS_HSYNC_B 0x61008
1117 #define _TRANS_VTOTAL_B 0x6100c
1118 #define _TRANS_VBLANK_B 0x61010
1119 #define _TRANS_VSYNC_B 0x61014
1120 #define _PIPEBSRC 0x6101c
1121 #define _BCLRPAT_B 0x61020
1122 #define _TRANS_VSYNCSHIFT_B 0x61028
1123 #define _TRANS_MULT_B 0x6102c
1125 /* DSI 0 timing regs */
1126 #define _TRANS_HTOTAL_DSI0 0x6b000
1127 #define _TRANS_HSYNC_DSI0 0x6b008
1128 #define _TRANS_VTOTAL_DSI0 0x6b00c
1129 #define _TRANS_VSYNC_DSI0 0x6b014
1130 #define _TRANS_VSYNCSHIFT_DSI0 0x6b028
1133 #define _TRANS_HTOTAL_DSI1 0x6b800
1134 #define _TRANS_HSYNC_DSI1 0x6b808
1135 #define _TRANS_VTOTAL_DSI1 0x6b80c
1136 #define _TRANS_VSYNC_DSI1 0x6b814
1137 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828
1151 #define ADPA _MMIO(0x61100)
1152 #define PCH_ADPA _MMIO(0xe1100)
1153 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
1156 #define ADPA_DAC_DISABLE 0
1163 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1164 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
1169 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
1171 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
1173 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
1175 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
1179 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
1183 #define ADPA_SETS_HVPOLARITY 0
1185 #define ADPA_VSYNC_CNTL_ENABLE 0
1187 #define ADPA_HSYNC_CNTL_ENABLE 0
1189 #define ADPA_VSYNC_ACTIVE_LOW 0
1191 #define ADPA_HSYNC_ACTIVE_LOW 0
1193 #define ADPA_DPMS_ON (0 << 10)
1200 #define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
1215 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1218 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1220 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1225 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1227 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1230 #define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
1250 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1285 #define _GEN3_SDVOB 0x61140
1286 #define _GEN3_SDVOC 0x61160
1291 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
1292 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
1293 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
1294 #define PCH_SDVOB _MMIO(0xe1140)
1296 #define PCH_HDMIC _MMIO(0xe1150)
1297 #define PCH_HDMID _MMIO(0xe1160)
1299 #define PORT_DFT_I9XX _MMIO(0x61150)
1301 #define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
1303 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
1306 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
1335 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
1337 #define SDVO_ENCODING_SDVO (0 << 10)
1340 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
1362 #define VIDEO_DIP_DATA _MMIO(0x61178)
1371 #define VIDEO_DIP_CTL _MMIO(0x61170)
1381 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1386 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1393 #define VSC_SELECT_MASK (0x3 << 25)
1395 #define VSC_DIP_HW_HEA_DATA (0 << 25)
1405 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
1410 #define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
1415 #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
1420 #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
1431 #define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
1437 #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
1439 #define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
1441 #define PCH_GTC_CTL _MMIO(0xe7000)
1445 #define DP_A _MMIO(0x64000) /* eDP */
1446 #define DP_B _MMIO(0x64100)
1447 #define DP_C _MMIO(0x64200)
1448 #define DP_D _MMIO(0x64300)
1450 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
1451 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
1452 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
1466 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1474 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
1482 #define DP_VOLTAGE_0_4 (0 << 25)
1492 #define DP_PRE_EMPHASIS_0 (0 << 22)
1508 #define DP_PLL_FREQ_270MHZ (0 << 16)
1550 #define _PIPEA_DATA_M_G4X 0x70050
1551 #define _PIPEB_DATA_M_G4X 0x71050
1553 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1557 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
1558 #define DATA_LINK_N_MAX (0x800000)
1560 #define _PIPEA_DATA_N_G4X 0x70054
1561 #define _PIPEB_DATA_N_G4X 0x71054
1574 #define _PIPEA_LINK_M_G4X 0x70060
1575 #define _PIPEB_LINK_M_G4X 0x71060
1576 #define _PIPEA_LINK_N_G4X 0x70064
1577 #define _PIPEB_LINK_N_G4X 0x71064
1585 #define _PIPEADSL 0x70000
1587 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
1588 #define _TRANSACONF 0x70008
1594 …CONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
1599 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
1605 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
1616 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
1629 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* il…
1634 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
1640 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
1644 #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
1647 #define _PIPEASTAT 0x70024
1692 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
1693 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
1695 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
1696 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
1704 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
1708 #define _PIPE_MISC_A 0x70030
1709 #define _PIPE_MISC_B 0x71030
1727 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
1733 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
1739 #define _PIPE_MISC2_A 0x7002C
1740 #define _PIPE_MISC2_B 0x7102C
1744 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1748 #define _ICL_PIPE_A_STATUS 0x70058
1755 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
1776 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
1791 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
1792 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
1804 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
1806 #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
1807 #define DSPARB_CSTART_MASK (0x7f << 7)
1809 #define DSPARB_BSTART_MASK (0x7f)
1810 #define DSPARB_BSTART_SHIFT 0
1812 #define DSPARB_AEND_SHIFT 0
1813 #define DSPARB_SPRITEA_SHIFT_VLV 0
1814 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
1816 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
1818 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
1820 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
1821 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
1822 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
1823 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
1825 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
1827 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
1829 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
1831 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
1833 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
1834 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
1835 #define DSPARB_SPRITEE_SHIFT_VLV 0
1836 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
1838 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
1841 #define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
1843 #define DSPFW_SR_MASK (0x1ff << 23)
1845 #define DSPFW_CURSORB_MASK (0x3f << 16)
1847 #define DSPFW_PLANEB_MASK (0x7f << 8)
1848 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
1849 #define DSPFW_PLANEA_SHIFT 0
1850 #define DSPFW_PLANEA_MASK (0x7f << 0)
1851 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
1852 #define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
1855 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
1857 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
1859 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
1860 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
1862 #define DSPFW_CURSORA_MASK (0x3f << 8)
1863 #define DSPFW_PLANEC_OLD_SHIFT 0
1864 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
1865 #define DSPFW_SPRITEA_SHIFT 0
1866 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
1867 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
1868 #define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
1872 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
1874 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
1875 #define DSPFW_HPLL_SR_SHIFT 0
1876 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
1879 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
1881 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
1883 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
1884 #define DSPFW_SPRITEA_WM1_SHIFT 0
1885 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
1886 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
1888 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
1890 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
1892 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
1893 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
1894 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
1895 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
1896 #define DSPFW_SR_WM1_SHIFT 0
1897 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
1898 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
1899 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
1901 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
1903 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
1905 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
1906 #define DSPFW_SPRITEC_SHIFT 0
1907 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
1908 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
1910 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
1912 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
1914 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
1915 #define DSPFW_SPRITEE_SHIFT 0
1916 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
1917 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
1919 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
1921 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
1923 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
1924 #define DSPFW_CURSORC_SHIFT 0
1925 #define DSPFW_CURSORC_MASK (0x3f << 0)
1928 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
1947 #define DSPFW_PLANEA_HI_SHIFT 0
1948 #define DSPFW_PLANEA_HI_MASK (1 << 0)
1949 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
1968 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
1969 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
1972 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
1975 #define DDL_PLANE_SHIFT 0
1977 #define DDL_PRECISION_LOW (0 << 7)
1978 #define DRAIN_LATENCY_MASK 0x7f
1980 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
1984 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
2000 #define VALLEYVIEW_MAX_WM 0xff
2001 #define G4X_MAX_WM 0x3f
2002 #define I915_MAX_WM 0x3f
2006 #define PINEVIEW_MAX_WM 0x1ff
2007 #define PINEVIEW_DFT_WM 0x3f
2008 #define PINEVIEW_DFT_HPLLOFF_WM 0
2011 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2012 #define PINEVIEW_CURSOR_DFT_WM 0
2021 #define _WM0_PIPEA_ILK 0x45100
2022 #define _WM0_PIPEB_ILK 0x45104
2023 #define _WM0_PIPEC_IVB 0x45200
2024 #define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \
2028 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
2032 #define WM1_LP_ILK _MMIO(0x45108)
2033 #define WM2_LP_ILK _MMIO(0x4510c)
2034 #define WM3_LP_ILK _MMIO(0x45110)
2040 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
2046 #define WM1S_LP_ILK _MMIO(0x45120)
2047 #define WM2S_LP_IVB _MMIO(0x45124)
2048 #define WM3S_LP_IVB _MMIO(0x45128)
2050 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
2068 #define _PIPEAFRAMEHIGH 0x70040
2069 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2070 #define PIPE_FRAME_HIGH_SHIFT 0
2071 #define _PIPEAFRAMEPIXEL 0x70044
2072 #define PIPE_FRAME_LOW_MASK 0xff000000
2074 #define PIPE_PIXEL_MASK 0x00ffffff
2075 #define PIPE_PIXEL_SHIFT 0
2077 #define _PIPEA_FRMCOUNT_G4X 0x70040
2078 #define _PIPEA_FLIPCOUNT_G4X 0x70044
2083 #define _CHV_BLEND_A 0x60a00
2085 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
2088 #define _CHV_CANVAS_A 0x60a04
2091 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
2097 #define DISP_BASEADDR_MASK (0xfffff000)
2108 * [00:0f] all
2112 #define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
2113 #define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
2114 #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
2115 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
2117 /* ICL DSI 0 and 1 */
2118 #define _PIPEDSI0CONF 0x7b008
2119 #define _PIPEDSI1CONF 0x7b808
2123 #define VGACNTRL _MMIO(0x71400)
2128 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
2132 #define CPU_VGACNTRL _MMIO(0x41000)
2134 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
2136 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
2141 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
2142 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
2143 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
2144 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
2147 #define RR_HW_CTL _MMIO(0x45300)
2148 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2149 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2151 #define PCH_3DCGDIS0 _MMIO(0x46020)
2155 #define PCH_3DCGDIS1 _MMIO(0x46024)
2158 #define _PIPEA_DATA_M1 0x60030
2159 #define _PIPEA_DATA_N1 0x60034
2160 #define _PIPEA_DATA_M2 0x60038
2161 #define _PIPEA_DATA_N2 0x6003c
2162 #define _PIPEA_LINK_M1 0x60040
2163 #define _PIPEA_LINK_N1 0x60044
2164 #define _PIPEA_LINK_M2 0x60048
2165 #define _PIPEA_LINK_N2 0x6004c
2167 /* PIPEB timing regs are same start from 0x61000 */
2169 #define _PIPEB_DATA_M1 0x61030
2170 #define _PIPEB_DATA_N1 0x61034
2171 #define _PIPEB_DATA_M2 0x61038
2172 #define _PIPEB_DATA_N2 0x6103c
2173 #define _PIPEB_LINK_M1 0x61040
2174 #define _PIPEB_LINK_N1 0x61044
2175 #define _PIPEB_LINK_M2 0x61048
2176 #define _PIPEB_LINK_N2 0x6104c
2188 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2189 #define _PFA_CTL_1 0x68080
2190 #define _PFB_CTL_1 0x68880
2195 #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
2199 #define _PFA_WIN_SZ 0x68074
2200 #define _PFB_WIN_SZ 0x68874
2203 #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2205 #define _PFA_WIN_POS 0x68070
2206 #define _PFB_WIN_POS 0x68870
2209 #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
2211 #define _PFA_VSCALE 0x68084
2212 #define _PFB_VSCALE 0x68884
2213 #define _PFA_HSCALE 0x68090
2214 #define _PFB_HSCALE 0x68890
2225 #define _PS_1A_CTRL 0x68180
2226 #define _PS_2A_CTRL 0x68280
2227 #define _PS_1B_CTRL 0x68980
2228 #define _PS_2B_CTRL 0x68A80
2229 #define _PS_1C_CTRL 0x69180
2232 #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
2235 #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
2239 #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
2243 #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
2246 #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
2251 #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
2254 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-lin…
2263 #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
2277 #define _PS_PWR_GATE_1A 0x68160
2278 #define _PS_PWR_GATE_2A 0x68260
2279 #define _PS_PWR_GATE_1B 0x68960
2280 #define _PS_PWR_GATE_2B 0x68A60
2281 #define _PS_PWR_GATE_1C 0x69160
2284 #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
2288 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
2289 #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
2294 #define _PS_WIN_POS_1A 0x68170
2295 #define _PS_WIN_POS_2A 0x68270
2296 #define _PS_WIN_POS_1B 0x68970
2297 #define _PS_WIN_POS_2B 0x68A70
2298 #define _PS_WIN_POS_1C 0x69170
2301 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
2304 #define _PS_WIN_SZ_1A 0x68174
2305 #define _PS_WIN_SZ_2A 0x68274
2306 #define _PS_WIN_SZ_1B 0x68974
2307 #define _PS_WIN_SZ_2B 0x68A74
2308 #define _PS_WIN_SZ_1C 0x69174
2311 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2314 #define _PS_VSCALE_1A 0x68184
2315 #define _PS_VSCALE_2A 0x68284
2316 #define _PS_VSCALE_1B 0x68984
2317 #define _PS_VSCALE_2B 0x68A84
2318 #define _PS_VSCALE_1C 0x69184
2320 #define _PS_HSCALE_1A 0x68190
2321 #define _PS_HSCALE_2A 0x68290
2322 #define _PS_HSCALE_1B 0x68990
2323 #define _PS_HSCALE_2B 0x68A90
2324 #define _PS_HSCALE_1C 0x69190
2326 #define _PS_VPHASE_1A 0x68188
2327 #define _PS_VPHASE_2A 0x68288
2328 #define _PS_VPHASE_1B 0x68988
2329 #define _PS_VPHASE_2B 0x68A88
2330 #define _PS_VPHASE_1C 0x69188
2333 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
2335 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
2336 #define PS_PHASE_TRIP (1 << 0)
2338 #define _PS_HPHASE_1A 0x68194
2339 #define _PS_HPHASE_2A 0x68294
2340 #define _PS_HPHASE_1B 0x68994
2341 #define _PS_HPHASE_2B 0x68A94
2342 #define _PS_HPHASE_1C 0x69194
2344 #define _PS_ECC_STAT_1A 0x681D0
2345 #define _PS_ECC_STAT_2A 0x682D0
2346 #define _PS_ECC_STAT_1B 0x689D0
2347 #define _PS_ECC_STAT_2B 0x68AD0
2348 #define _PS_ECC_STAT_1C 0x691D0
2350 #define _PS_COEF_SET0_INDEX_1A 0x68198
2351 #define _PS_COEF_SET0_INDEX_2A 0x68298
2352 #define _PS_COEF_SET0_INDEX_1B 0x68998
2353 #define _PS_COEF_SET0_INDEX_2B 0x68A98
2356 #define _PS_COEF_SET0_DATA_1A 0x6819C
2357 #define _PS_COEF_SET0_DATA_2A 0x6829C
2358 #define _PS_COEF_SET0_DATA_1B 0x6899C
2359 #define _PS_COEF_SET0_DATA_2B 0x68A9C
2398 #define RM_TIMEOUT _MMIO(0x42060)
2399 #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
2400 #define MMIO_TIMEOUT_US(us) ((us) << 0)
2432 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2451 #define DE_PIPEA_VBLANK_IVB (1 << 0)
2454 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
2457 #define DEISR _MMIO(0x44000)
2458 #define DEIMR _MMIO(0x44004)
2459 #define DEIIR _MMIO(0x44008)
2460 #define DEIER _MMIO(0x4400c)
2462 #define GTISR _MMIO(0x44010)
2463 #define GTIMR _MMIO(0x44014)
2464 #define GTIIR _MMIO(0x44018)
2465 #define GTIER _MMIO(0x4401c)
2467 #define GEN8_MASTER_IRQ _MMIO(0x44200)
2483 #define GEN8_GT_RCS_IRQ (1 << 0)
2485 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
2487 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
2488 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
2489 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
2490 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
2492 #define GEN8_RCS_IRQ_SHIFT 0
2494 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
2496 #define GEN8_VECS_IRQ_SHIFT 0
2499 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
2500 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
2501 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
2502 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
2541 #define GEN8_PIPE_VBLANK REG_BIT(0)
2546 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
2547 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
2548 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
2549 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
2565 #define GEN8_AUX_CHANNEL_A (1 << 0)
2576 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
2578 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
2579 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
2580 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
2581 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
2588 #define GEN8_PCU_ISR _MMIO(0x444e0)
2589 #define GEN8_PCU_IMR _MMIO(0x444e4)
2590 #define GEN8_PCU_IIR _MMIO(0x444e8)
2591 #define GEN8_PCU_IER _MMIO(0x444ec)
2593 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
2594 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
2595 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
2596 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
2599 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
2606 #define GEN11_GT_DW0_IRQ (1 << 0)
2608 #define DG1_MSTR_TILE_INTR _MMIO(0x190008)
2612 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
2623 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
2624 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
2625 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
2626 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
2642 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
2643 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
2647 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
2649 #define PICAINTERRUPT_ISR _MMIO(0x16FE50)
2650 #define PICAINTERRUPT_IMR _MMIO(0x16FE54)
2651 #define PICAINTERRUPT_IIR _MMIO(0x16FE58)
2652 #define PICAINTERRUPT_IER _MMIO(0x16FE5C)
2660 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
2662 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
2668 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
2670 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
2676 #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
2682 #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
2684 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
2687 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
2693 #define FUSE_STRAP _MMIO(0x42014)
2704 #define FUSE_STRAP3 _MMIO(0x42020)
2707 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
2714 #define IVB_CHICKEN3 _MMIO(0x4200c)
2718 #define CHICKEN_PAR1_1 _MMIO(0x42080)
2728 #define CHICKEN_PAR2_1 _MMIO(0x42090)
2731 #define CHICKEN_MISC_2 _MMIO(0x42084)
2740 #define CHICKEN_MISC_3 _MMIO(0x42088)
2743 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2745 #define CHICKEN_MISC_4 _MMIO(0x4208c)
2747 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
2750 #define _CHICKEN_PIPESL_1_A 0x420b0
2751 #define _CHICKEN_PIPESL_1_B 0x420b4
2754 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
2759 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
2766 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
2767 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
2771 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
2773 #define _CHICKEN_TRANS_A 0x420c0
2774 #define _CHICKEN_TRANS_B 0x420c4
2775 #define _CHICKEN_TRANS_C 0x420c8
2776 #define _CHICKEN_TRANS_EDP 0x420cc
2777 #define _CHICKEN_TRANS_D 0x420d8
2784 #define _MTL_CHICKEN_TRANS_A 0x604e0
2785 #define _MTL_CHICKEN_TRANS_B 0x614e0
2804 #define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
2806 #define DISP_ARB_CTL _MMIO(0x45000)
2811 #define DISP_ARB_CTL2 _MMIO(0x45004)
2815 #define GEN7_MSG_CTL _MMIO(0x45010)
2817 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
2819 #define _BW_BUDDY0_CTL 0x45130
2820 #define _BW_BUDDY1_CTL 0x45140
2828 #define _BW_BUDDY0_PAGE_MASK 0x45134
2829 #define _BW_BUDDY1_PAGE_MASK 0x45144
2834 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
2838 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
2849 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
2855 #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
2858 #define SKL_DFSM _MMIO(0x51000)
2862 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
2873 #define XE2LPD_DE_CAP _MMIO(0x41100)
2880 #define SKL_DSSM _MMIO(0x51004)
2882 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
2886 #define GMD_ID_DISPLAY _MMIO(0x510a0)
2889 #define GMD_ID_STEP REG_GENMASK(5, 0)
2892 #define _PIPEA_CHICKEN 0x70038
2893 #define _PIPEB_CHICKEN 0x71038
2894 #define _PIPEC_CHICKEN 0x72038
2905 #define PCH_DISPLAY_BASE 0xc0000u
2945 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
2946 #define SDE_TRANS_MASK (0x3f)
2985 #define SDE_FDI_RXA_CPT (1 << 0)
3013 #define SDEISR _MMIO(0xc4000)
3014 #define SDEIMR _MMIO(0xc4004)
3015 #define SDEIIR _MMIO(0xc4008)
3016 #define SDEIER _MMIO(0xc400c)
3018 #define SERR_INT _MMIO(0xc4040)
3023 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
3027 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
3031 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
3037 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
3042 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
3048 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
3053 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
3058 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
3059 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
3060 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3061 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
3066 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
3068 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
3069 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
3070 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
3071 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
3078 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
3079 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
3080 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
3081 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
3082 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
3083 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
3084 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
3085 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
3087 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
3092 #define SHPD_FILTER_CNT _MMIO(0xc4038)
3093 #define SHPD_FILTER_CNT_500_ADJ 0x001D9
3094 #define SHPD_FILTER_CNT_250 0x000F8
3096 #define _PCH_DPLL_A 0xc6014
3097 #define _PCH_DPLL_B 0xc6018
3098 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3100 #define _PCH_FPA0 0xc6040
3101 #define FP_CB_TUNE (0x3 << 22)
3102 #define _PCH_FPA1 0xc6044
3103 #define _PCH_FPB0 0xc6048
3104 #define _PCH_FPB1 0xc604c
3105 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
3106 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
3108 #define PCH_DPLL_TEST _MMIO(0xc606c)
3110 #define PCH_DREF_CONTROL _MMIO(0xC6200)
3111 #define DREF_CONTROL_MASK 0x7fc3
3112 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
3116 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
3119 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
3123 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
3126 #define DREF_SSC4_DOWNSPREAD (0 << 6)
3128 #define DREF_SSC1_DISABLE (0 << 1)
3130 #define DREF_SSC4_DISABLE (0)
3133 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
3138 #define RAWCLK_FREQ_MASK 0x3ff
3139 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
3141 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
3145 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
3147 #define PCH_SSC4_PARMS _MMIO(0xc6210)
3148 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
3150 #define PCH_DPLL_SEL _MMIO(0xc7000)
3152 #define TRANS_DPLLA_SEL(pipe) 0
3157 #define _PCH_TRANS_HTOTAL_A 0xe0000
3159 #define TRANS_HACTIVE_SHIFT 0
3160 #define _PCH_TRANS_HBLANK_A 0xe0004
3162 #define TRANS_HBLANK_START_SHIFT 0
3163 #define _PCH_TRANS_HSYNC_A 0xe0008
3165 #define TRANS_HSYNC_START_SHIFT 0
3166 #define _PCH_TRANS_VTOTAL_A 0xe000c
3168 #define TRANS_VACTIVE_SHIFT 0
3169 #define _PCH_TRANS_VBLANK_A 0xe0010
3171 #define TRANS_VBLANK_START_SHIFT 0
3172 #define _PCH_TRANS_VSYNC_A 0xe0014
3174 #define TRANS_VSYNC_START_SHIFT 0
3175 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
3177 #define _PCH_TRANSA_DATA_M1 0xe0030
3178 #define _PCH_TRANSA_DATA_N1 0xe0034
3179 #define _PCH_TRANSA_DATA_M2 0xe0038
3180 #define _PCH_TRANSA_DATA_N2 0xe003c
3181 #define _PCH_TRANSA_LINK_M1 0xe0040
3182 #define _PCH_TRANSA_LINK_N1 0xe0044
3183 #define _PCH_TRANSA_LINK_M2 0xe0048
3184 #define _PCH_TRANSA_LINK_N2 0xe004c
3187 #define _VIDEO_DIP_CTL_A 0xe0200
3188 #define _VIDEO_DIP_DATA_A 0xe0208
3189 #define _VIDEO_DIP_GCP_A 0xe0210
3192 #define GCP_AV_MUTE (1 << 0)
3194 #define _VIDEO_DIP_CTL_B 0xe1200
3195 #define _VIDEO_DIP_DATA_B 0xe1208
3196 #define _VIDEO_DIP_GCP_B 0xe1210
3203 #define _VLV_VIDEO_DIP_CTL_A 0x60200
3204 #define _VLV_VIDEO_DIP_CTL_B 0x61170
3205 #define _CHV_VIDEO_DIP_CTL_C 0x611f0
3211 #define _VLV_VIDEO_DIP_DATA_A 0x60208
3212 #define _VLV_VIDEO_DIP_DATA_B 0x61174
3213 #define _CHV_VIDEO_DIP_DATA_C 0x611f4
3219 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
3220 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
3221 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
3229 #define _HSW_VIDEO_DIP_CTL_A 0x60200
3230 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
3231 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
3232 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
3233 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
3234 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
3235 #define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
3236 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
3237 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
3238 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
3239 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
3240 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
3241 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
3242 #define _HSW_VIDEO_DIP_GCP_A 0x60210
3244 #define _HSW_VIDEO_DIP_CTL_B 0x61200
3245 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
3246 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
3247 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
3248 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
3249 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
3250 #define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
3251 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
3252 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
3253 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
3254 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
3255 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
3256 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3257 #define _HSW_VIDEO_DIP_GCP_B 0x61210
3265 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
3266 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
3267 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
3268 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
3284 #define _HSW_STEREO_3D_CTL_A 0x70020
3286 #define _HSW_STEREO_3D_CTL_B 0x71020
3290 #define _PCH_TRANS_HTOTAL_B 0xe1000
3291 #define _PCH_TRANS_HBLANK_B 0xe1004
3292 #define _PCH_TRANS_HSYNC_B 0xe1008
3293 #define _PCH_TRANS_VTOTAL_B 0xe100c
3294 #define _PCH_TRANS_VBLANK_B 0xe1010
3295 #define _PCH_TRANS_VSYNC_B 0xe1014
3296 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
3306 #define _PCH_TRANSB_DATA_M1 0xe1030
3307 #define _PCH_TRANSB_DATA_N1 0xe1034
3308 #define _PCH_TRANSB_DATA_M2 0xe1038
3309 #define _PCH_TRANSB_DATA_N2 0xe103c
3310 #define _PCH_TRANSB_LINK_M1 0xe1040
3311 #define _PCH_TRANSB_LINK_N1 0xe1044
3312 #define _PCH_TRANSB_LINK_M2 0xe1048
3313 #define _PCH_TRANSB_LINK_N2 0xe104c
3324 #define _PCH_TRANSACONF 0xf0008
3325 #define _PCH_TRANSBCONF 0xf1008
3331 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
3333 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
3337 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
3342 #define _TRANSA_CHICKEN1 0xf0060
3343 #define _TRANSB_CHICKEN1 0xf1060
3348 #define _TRANSA_CHICKEN2 0xf0064
3349 #define _TRANSB_CHICKEN2 0xf1064
3354 …CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
3358 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
3374 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
3378 #define SPT_PWM_GRANULARITY (1 << 0)
3379 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
3383 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
3385 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
3394 #define PCH_DP_B _MMIO(0xe4100)
3395 #define PCH_DP_C _MMIO(0xe4200)
3396 #define PCH_DP_D _MMIO(0xe4300)
3399 #define _TRANS_DP_CTL_A 0xe0300
3400 #define _TRANS_DP_CTL_B 0xe1300
3401 #define _TRANS_DP_CTL_C 0xe2300
3410 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
3417 #define _TRANS_DP2_CTL_A 0x600a0
3418 #define _TRANS_DP2_CTL_B 0x610a0
3419 #define _TRANS_DP2_CTL_C 0x620a0
3420 #define _TRANS_DP2_CTL_D 0x630a0
3426 #define _TRANS_DP2_VFREQHIGH_A 0x600a4
3427 #define _TRANS_DP2_VFREQHIGH_B 0x610a4
3428 #define _TRANS_DP2_VFREQHIGH_C 0x620a4
3429 #define _TRANS_DP2_VFREQHIGH_D 0x630a4
3434 #define _TRANS_DP2_VFREQLOW_A 0x600a8
3435 #define _TRANS_DP2_VFREQLOW_B 0x610a8
3436 #define _TRANS_DP2_VFREQLOW_C 0x620a8
3437 #define _TRANS_DP2_VFREQLOW_D 0x630a8
3442 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
3443 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
3444 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
3445 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
3447 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
3448 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
3449 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
3450 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
3451 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
3452 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
3455 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
3456 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
3457 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
3458 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
3459 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
3460 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
3461 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
3464 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
3465 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
3466 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
3467 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
3468 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
3470 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
3472 #define VLV_PMWGICZ _MMIO(0x1300a4)
3474 #define HSW_EDRAM_CAP _MMIO(0x120010)
3475 #define EDRAM_ENABLED 0x1
3476 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
3477 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
3478 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
3480 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
3484 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
3488 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
3489 #define GEN6_PCODE_ERROR_MASK 0xFF
3490 #define GEN6_PCODE_SUCCESS 0x0
3491 #define GEN6_PCODE_ILLEGAL_CMD 0x1
3492 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
3493 #define GEN6_PCODE_TIMEOUT 0x3
3494 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
3495 #define GEN7_PCODE_TIMEOUT 0x2
3496 #define GEN7_PCODE_ILLEGAL_DATA 0x3
3497 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
3498 #define GEN11_PCODE_LOCKED 0x6
3499 #define GEN11_PCODE_REJECTED 0x11
3500 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
3501 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
3502 #define GEN6_PCODE_READ_RC6VIDS 0x5
3505 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
3506 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
3510 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
3511 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
3512 #define SKL_PCODE_CDCLK_CONTROL 0x7
3513 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
3514 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
3515 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3516 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3517 #define GEN6_READ_OC_PARAMS 0xc
3518 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
3519 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
3520 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
3521 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
3522 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
3523 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
3536 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
3537 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
3538 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
3542 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
3545 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
3549 #define GEN6_PCODE_READ_D_COMP 0x10
3550 #define GEN6_PCODE_WRITE_D_COMP 0x11
3551 #define ICL_PCODE_EXIT_TCCOLD 0x12
3552 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
3553 #define DISPLAY_IPS_CONTROL 0x19
3554 #define TGL_PCODE_TCCOLD 0x26
3555 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
3556 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
3557 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
3560 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
3561 #define GEN9_PCODE_SAGV_CONTROL 0x21
3562 #define GEN9_SAGV_DISABLE 0x0
3563 #define GEN9_SAGV_IS_DISABLED 0x1
3564 #define GEN9_SAGV_ENABLE 0x3
3565 #define DG1_PCODE_STATUS 0x7E
3566 #define DG1_UNCORE_GET_INIT_STATUS 0x0
3567 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
3568 #define PCODE_POWER_SETUP 0x7C
3569 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
3570 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
3573 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
3574 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
3575 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
3577 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
3578 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
3581 #define PCODE_MBOX_DOMAIN_NONE 0x0
3582 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
3583 #define GEN6_PCODE_DATA _MMIO(0x138128)
3586 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
3588 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
3589 #define STOLEN_ACCESS_ALLOWED 0x1
3592 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
3593 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
3609 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
3626 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
3627 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
3628 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
3629 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
3630 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
3631 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
3647 #define SKL_PW_CTL_IDX_MISC_IO 0
3654 #define ICL_PW_CTL_IDX_PW_1 0
3662 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
3663 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
3664 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
3688 #define ICL_PW_CTL_IDX_AUX_A 0
3690 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
3691 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
3692 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
3706 #define ICL_PW_CTL_IDX_DDI_A 0
3709 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
3713 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
3724 #define SKL_FUSE_STATUS _MMIO(0x42000)
3741 #define _TRANS_DDI_FUNC_CTL_A 0x60400
3742 #define _TRANS_DDI_FUNC_CTL_B 0x61400
3743 #define _TRANS_DDI_FUNC_CTL_C 0x62400
3744 #define _TRANS_DDI_FUNC_CTL_D 0x63400
3745 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
3746 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
3747 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
3755 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
3759 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
3765 #define TRANS_DDI_BPC_8 (0 << 20)
3775 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
3793 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
3798 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
3799 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
3800 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
3801 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
3802 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
3803 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
3806 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
3809 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
3813 #define _DP_TP_CTL_A 0x64040
3814 #define _DP_TP_CTL_B 0x64140
3815 #define _TGL_DP_TP_CTL_A 0x60540
3820 #define DP_TP_CTL_MODE_SST (0 << 27)
3824 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19)
3830 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
3839 #define _DP_TP_STATUS_A 0x64044
3840 #define _DP_TP_STATUS_B 0x64144
3841 #define _TGL_DP_TP_STATUS_A 0x60544
3851 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
3854 #define _DDI_BUF_CTL_A 0x64000
3855 #define _DDI_BUF_CTL_B 0x64100
3862 #define DDI_BUF_EMP_MASK (0xf << 24)
3865 #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
3875 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
3878 #define _DDI_BUF_TRANS_A 0x64E00
3879 #define _DDI_BUF_TRANS_B 0x64E60
3885 #define _DDI_DP_COMP_CTL_A 0x605F0
3886 #define _DDI_DP_COMP_CTL_B 0x615F0
3889 #define DDI_DP_COMP_CTL_D10_2 (0 << 28)
3895 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
3898 #define _DDI_DP_COMP_PAT_A 0x605F4
3899 #define _DDI_DP_COMP_PAT_B 0x615F4
3905 #define SBI_ADDR _MMIO(0xC6000)
3906 #define SBI_DATA _MMIO(0xC6004)
3907 #define SBI_CTL_STAT _MMIO(0xC6008)
3908 #define SBI_CTL_DEST_ICLK (0x0 << 16)
3909 #define SBI_CTL_DEST_MPHY (0x1 << 16)
3910 #define SBI_CTL_OP_IORD (0x2 << 8)
3911 #define SBI_CTL_OP_IOWR (0x3 << 8)
3912 #define SBI_CTL_OP_CRRD (0x6 << 8)
3913 #define SBI_CTL_OP_CRWR (0x7 << 8)
3914 #define SBI_RESPONSE_FAIL (0x1 << 1)
3915 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
3916 #define SBI_BUSY (0x1 << 0)
3917 #define SBI_READY (0x0 << 0)
3920 #define SBI_SSCDIVINTPHASE 0x0200
3921 #define SBI_SSCDIVINTPHASE6 0x0600
3923 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
3926 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
3929 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
3930 #define SBI_SSCDITHPHASE 0x0204
3931 #define SBI_SSCCTL 0x020c
3932 #define SBI_SSCCTL6 0x060C
3934 #define SBI_SSCCTL_DISABLE (1 << 0)
3935 #define SBI_SSCAUXDIV6 0x0610
3939 #define SBI_DBUFF0 0x2a00
3940 #define SBI_GEN0 0x1f00
3941 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
3944 #define PIXCLK_GATE _MMIO(0xC6020)
3945 #define PIXCLK_GATE_UNGATE (1 << 0)
3946 #define PIXCLK_GATE_GATE (0 << 0)
3949 #define SPLL_CTL _MMIO(0x46020)
3951 #define SPLL_REF_BCLK (0 << 28)
3957 #define SPLL_FREQ_810MHz (0 << 26)
3963 #define _WRPLL_CTL1 0x46040
3964 #define _WRPLL_CTL2 0x46060
3967 #define WRPLL_REF_BCLK (0 << 28)
3974 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
3975 #define WRPLL_DIVIDER_REF_MASK (0xff)
3977 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
3981 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
3984 #define _PORT_CLK_SEL_A 0x46100
3985 #define _PORT_CLK_SEL_B 0x46104
3988 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
4000 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
4001 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
4002 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
4003 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
4004 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
4005 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
4008 #define _TRANS_CLK_SEL_A 0x46140
4009 #define _TRANS_CLK_SEL_B 0x46144
4012 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
4014 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
4018 #define CDCLK_FREQ _MMIO(0x46200)
4020 #define _TRANSA_MSA_MISC 0x60410
4021 #define _TRANSB_MSA_MISC 0x61410
4022 #define _TRANSC_MSA_MISC 0x62410
4023 #define _TRANS_EDP_MSA_MISC 0x6f410
4027 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
4028 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
4029 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
4030 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
4032 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
4036 #define LCPLL_CTL _MMIO(0x130040)
4039 #define LCPLL_REF_NON_SSC (0 << 28)
4044 #define LCPLL_CLK_FREQ_450 (0 << 26)
4060 #define CDCLK_CTL _MMIO(0x46000)
4062 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
4067 #define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
4070 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
4077 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
4082 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
4085 #define CDCLK_SQUASH_CTL _MMIO(0x46008)
4089 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
4093 #define LCPLL1_CTL _MMIO(0x46010)
4094 #define LCPLL2_CTL _MMIO(0x46014)
4098 #define DPLL_CTRL1 _MMIO(0x6C058)
4105 #define DPLL_CTRL1_LINK_RATE_2700 0
4113 #define DPLL_CTRL2 _MMIO(0x6C05C)
4121 #define DPLL_STATUS _MMIO(0x6C060)
4125 #define _DPLL1_CFGCR1 0x6C040
4126 #define _DPLL2_CFGCR1 0x6C048
4127 #define _DPLL3_CFGCR1 0x6C050
4129 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
4131 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
4133 #define _DPLL1_CFGCR2 0x6C044
4134 #define _DPLL2_CFGCR2 0x6C04C
4135 #define _DPLL3_CFGCR2 0x6C054
4136 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
4141 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
4147 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
4158 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
4167 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
4179 #define _DG1_DPCLKA_CFGCR0 0x164280
4180 #define _DG1_DPCLKA1_CFGCR0 0x16C280
4189 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4192 #define _ADLS_DPCLKA_CFGCR0 0x164280
4193 #define _ADLS_DPCLKA_CFGCR1 0x1642BC
4201 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
4204 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
4213 #define _DPLL0_ENABLE 0x46010
4214 #define _DPLL1_ENABLE 0x46014
4215 #define _ADLS_DPLL2_ENABLE 0x46018
4216 #define _ADLS_DPLL3_ENABLE 0x46030
4225 #define _DG2_PLL3_ENABLE 0x4601C
4231 #define TBT_PLL_ENABLE _MMIO(0x46020)
4233 #define _MG_PLL1_ENABLE 0x46030
4234 #define _MG_PLL2_ENABLE 0x46034
4235 #define _MG_PLL3_ENABLE 0x46038
4236 #define _MG_PLL4_ENABLE 0x4603C
4247 #define PORTTC1_PLL_ENABLE 0x46038
4248 #define PORTTC2_PLL_ENABLE 0x46040
4254 #define _ICL_DPLL0_CFGCR0 0x164000
4255 #define _ICL_DPLL1_CFGCR0 0x164080
4261 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
4262 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
4270 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
4273 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
4275 #define _ICL_DPLL0_CFGCR1 0x164004
4276 #define _ICL_DPLL1_CFGCR1 0x164084
4279 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
4290 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
4297 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
4298 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
4299 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
4301 #define _TGL_DPLL0_CFGCR0 0x164284
4302 #define _TGL_DPLL1_CFGCR0 0x16428C
4303 #define _TGL_TBTPLL_CFGCR0 0x16429C
4310 #define _TGL_DPLL0_DIV0 0x164B00
4311 #define _TGL_DPLL1_DIV0 0x164C00
4316 #define _TGL_DPLL0_CFGCR1 0x164288
4317 #define _TGL_DPLL1_CFGCR1 0x164290
4318 #define _TGL_TBTPLL_CFGCR1 0x1642A0
4325 #define _DG1_DPLL2_CFGCR0 0x16C284
4326 #define _DG1_DPLL3_CFGCR0 0x16C28C
4331 #define _DG1_DPLL2_CFGCR1 0x16C288
4332 #define _DG1_DPLL3_CFGCR1 0x16C290
4338 #define _ADLS_DPLL4_CFGCR0 0x164294
4339 #define _ADLS_DPLL3_CFGCR0 0x1642C0
4344 #define _ADLS_DPLL4_CFGCR1 0x164298
4345 #define _ADLS_DPLL3_CFGCR1 0x1642C4
4351 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
4353 #define BXT_DE_PLL_RATIO_MASK 0xff
4355 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
4361 #define ICL_CDCLK_PLL_RATIO_MASK 0xff
4364 #define DC_STATE_EN _MMIO(0x45504)
4365 #define DC_STATE_DISABLE 0
4370 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
4372 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
4373 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
4375 #define DC_STATE_DEBUG _MMIO(0x45520)
4376 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
4379 #define D_COMP_BDW _MMIO(0x138144)
4382 #define _WM_LINETIME_A 0x45270
4383 #define _WM_LINETIME_B 0x45274
4385 #define HSW_LINETIME_MASK REG_GENMASK(8, 0)
4391 #define SFUSE_STRAP _MMIO(0xc2014)
4399 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
4401 #define WM_MISC _MMIO(0x45260)
4402 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
4404 #define WM_DBG _MMIO(0x45280)
4405 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
4410 #define GEN4_TIMESTAMP _MMIO(0x2358)
4411 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
4412 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
4414 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
4415 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
4416 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
4418 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
4421 #define _PIPE_FRMTMSTMP_A 0x70048
4422 #define _PIPE_FRMTMSTMP_B 0x71048
4427 #define _PIPE_FLIPTMSTMP_A 0x7004C
4428 #define _PIPE_FLIPTMSTMP_B 0x7104C
4433 #define _PIPE_FLIPDONETMSTMP_A 0x70054
4434 #define _PIPE_FLIPDONETMSTMP_B 0x71054
4438 #define _VLV_PIPE_MSA_MISC_A 0x70048
4442 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
4444 #define GGC _MMIO(0x108040)
4448 #define GEN6_GSMBASE _MMIO(0x108100)
4449 #define GEN6_DSMBASE _MMIO(0x1080C0)
4453 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
4458 #define _ICL_PHY_MISC_A 0x64C00
4459 #define _ICL_PHY_MISC_B 0x64C04
4460 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
4468 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
4473 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
4476 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
4479 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
4482 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
4484 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
4487 #define _TCSS_DDI_STATUS_1 0x161500
4488 #define _TCSS_DDI_STATUS_2 0x161504
4495 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
4497 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
4498 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
4499 #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
4500 #define SPI_STATIC_REGIONS _MMIO(0x102090)
4501 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
4502 #define OROM_OFFSET _MMIO(0x1020c0)
4505 #define CLKREQ_POLICY _MMIO(0x101038)
4508 #define CLKGATE_DIS_MISC _MMIO(0x46534)
4511 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
4512 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
4516 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
4519 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
4521 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
4525 #define MTL_DCLK_MASK REG_GENMASK(15, 0)
4529 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
4531 #define MTL_MEDIA_GSI_BASE 0x380000