297 static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)  in hwm_pcode_read_i1()  argument
304 				POWER_SETUP_SUBCOMMAND_READ_I1, 0, uval);  in hwm_pcode_read_i1()
307 static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval)  in hwm_pcode_write_i1()  argument
310 				  POWER_SETUP_SUBCOMMAND_WRITE_I1, 0, uval);  in hwm_pcode_write_i1()
350 	u32 uval;  in hwm_power_is_visible()  local
358 		return (hwm_pcode_read_i1(i915, &uval) ||  in hwm_power_is_visible()
359 			!(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;  in hwm_power_is_visible()
468 	u32 uval;  in hwm_power_read()  local
481 		ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);  in hwm_power_read()
484 		if (!(uval & POWER_SETUP_I1_WATTS))  in hwm_power_read()
486 		*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),  in hwm_power_read()
497 	u32 uval;  in hwm_power_write()  local
503 		uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);  in hwm_power_write()
504 		return hwm_pcode_write_i1(ddat->uncore->i915, uval);  in hwm_power_write()
579 	u32 uval;  in hwm_curr_is_visible()  local
583 		return (hwm_pcode_read_i1(i915, &uval) ||  in hwm_curr_is_visible()
584 			(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;  in hwm_curr_is_visible()
594 	u32 uval;  in hwm_curr_read()  local
598 		ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);  in hwm_curr_read()
601 		if (uval & POWER_SETUP_I1_WATTS)  in hwm_curr_read()
603 		*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),  in hwm_curr_read()
614 	u32 uval;  in hwm_curr_write()  local
618 		uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);  in hwm_curr_write()
619 		return hwm_pcode_write_i1(ddat->uncore->i915, uval);  in hwm_curr_write()