Lines Matching refs:_MMIO

68 	(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
69 		(_MMIO(0x50090))) : \
70 	(((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
71 		(_MMIO(0x50098))) : \
72 	(((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
73 		(_MMIO(0x5009C))) : \
74 		(_MMIO(0x50080))))); })
114 #define PCH_GPIO_BASE	_MMIO(0xc5010)
116 #define PCH_GMBUS0	_MMIO(0xc5100)
117 #define PCH_GMBUS1	_MMIO(0xc5104)
118 #define PCH_GMBUS2	_MMIO(0xc5108)
119 #define PCH_GMBUS3	_MMIO(0xc510c)
120 #define PCH_GMBUS4	_MMIO(0xc5110)
121 #define PCH_GMBUS5	_MMIO(0xc5120)
123 #define TRVATTL3PTRDW(i)	_MMIO(0x4de0 + (i) * 4)
124 #define TRNULLDETCT		_MMIO(0x4de8)
125 #define TRINVTILEDETCT		_MMIO(0x4dec)
126 #define TRVADR			_MMIO(0x4df0)
127 #define TRTTE			_MMIO(0x4df4)
128 #define RING_EXCC(base)		_MMIO((base) + 0x28)
129 #define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
130 #define VF_GUARDBAND		_MMIO(0x83a4)
135 #define PCH_PP_STATUS  _MMIO(0xc7200)
136 #define PCH_PP_CONTROL _MMIO(0xc7204)
137 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
138 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
139 #define PCH_PP_DIVISOR _MMIO(0xc7210)