47  * @vgpu: a vGPU
53 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)  in intel_vgpu_gpa_to_mmio_offset()  argument
55 	u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);  in intel_vgpu_gpa_to_mmio_offset()
66 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,  in failsafe_emulate_mmio_rw()  argument
73 	if (!vgpu || !p_data)  in failsafe_emulate_mmio_rw()
76 	gvt = vgpu->gvt;  in failsafe_emulate_mmio_rw()
77 	mutex_lock(&vgpu->vgpu_lock);  in failsafe_emulate_mmio_rw()
78 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);  in failsafe_emulate_mmio_rw()
81 			intel_vgpu_default_mmio_read(vgpu, offset, p_data,  in failsafe_emulate_mmio_rw()
84 			intel_vgpu_default_mmio_write(vgpu, offset, p_data,  in failsafe_emulate_mmio_rw()
88 		pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;  in failsafe_emulate_mmio_rw()
95 	mutex_unlock(&vgpu->vgpu_lock);  in failsafe_emulate_mmio_rw()
100  * @vgpu: a vGPU
108 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,  in intel_vgpu_emulate_mmio_read()  argument
111 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_emulate_mmio_read()
116 	if (vgpu->failsafe) {  in intel_vgpu_emulate_mmio_read()
117 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
120 	mutex_lock(&vgpu->vgpu_lock);  in intel_vgpu_emulate_mmio_read()
122 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);  in intel_vgpu_emulate_mmio_read()
137 		ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,  in intel_vgpu_emulate_mmio_read()
145 		ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_read()
157 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
169 	mutex_unlock(&vgpu->vgpu_lock);  in intel_vgpu_emulate_mmio_read()
175  * @vgpu: a vGPU
183 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,  in intel_vgpu_emulate_mmio_write()  argument
186 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_emulate_mmio_write()
191 	if (vgpu->failsafe) {  in intel_vgpu_emulate_mmio_write()
192 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
196 	mutex_lock(&vgpu->vgpu_lock);  in intel_vgpu_emulate_mmio_write()
198 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);  in intel_vgpu_emulate_mmio_write()
213 		ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,  in intel_vgpu_emulate_mmio_write()
221 		ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_write()
225 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
236 	mutex_unlock(&vgpu->vgpu_lock);  in intel_vgpu_emulate_mmio_write()
243  * @vgpu: a vGPU
246 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)  in intel_vgpu_reset_mmio()  argument
248 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_reset_mmio()
253 		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);  in intel_vgpu_reset_mmio()
255 		vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;  in intel_vgpu_reset_mmio()
258 		vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;  in intel_vgpu_reset_mmio()
261 		vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;  in intel_vgpu_reset_mmio()
263 		if (IS_BROXTON(vgpu->gvt->gt->i915)) {  in intel_vgpu_reset_mmio()
264 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=  in intel_vgpu_reset_mmio()
266 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=  in intel_vgpu_reset_mmio()
268 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=  in intel_vgpu_reset_mmio()
270 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=  in intel_vgpu_reset_mmio()
272 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=  in intel_vgpu_reset_mmio()
274 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=  in intel_vgpu_reset_mmio()
276 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=  in intel_vgpu_reset_mmio()
279 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=  in intel_vgpu_reset_mmio()
281 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=  in intel_vgpu_reset_mmio()
284 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=  in intel_vgpu_reset_mmio()
286 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=  in intel_vgpu_reset_mmio()
289 			vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=  in intel_vgpu_reset_mmio()
301 		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);  in intel_vgpu_reset_mmio()
308  * @vgpu: a vGPU
313 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)  in intel_vgpu_init_mmio()  argument
315 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;  in intel_vgpu_init_mmio()
317 	vgpu->mmio.vreg = vzalloc(info->mmio_size);  in intel_vgpu_init_mmio()
318 	if (!vgpu->mmio.vreg)  in intel_vgpu_init_mmio()
321 	intel_vgpu_reset_mmio(vgpu, true);  in intel_vgpu_init_mmio()
328  * @vgpu: a vGPU
331 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)  in intel_vgpu_clean_mmio()  argument
333 	vfree(vgpu->mmio.vreg);  in intel_vgpu_clean_mmio()
334 	vgpu->mmio.vreg = NULL;  in intel_vgpu_clean_mmio()