Lines Matching +full:com +full:- +full:offset
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
25 * Kevin Tian <kevin.tian@intel.com>
29 * Tina Zhang <tina.zhang@intel.com>
30 * Min He <min.he@intel.com>
31 * Niu Bing <bing.niu@intel.com>
32 * Zhi Wang <zhi.a.wang@intel.com>
46 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
56 return gpa - gttmmio_gpa; in intel_vgpu_gpa_to_mmio_offset()
60 (reg >= 0 && reg < gvt->device_info.mmio_size)
63 (reg >= gvt->device_info.gtt_start_offset \
64 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
71 unsigned int offset = 0; in failsafe_emulate_mmio_rw() local
76 gvt = vgpu->gvt; in failsafe_emulate_mmio_rw()
77 mutex_lock(&vgpu->vgpu_lock); in failsafe_emulate_mmio_rw()
78 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); in failsafe_emulate_mmio_rw()
79 if (reg_is_mmio(gvt, offset)) { in failsafe_emulate_mmio_rw()
81 intel_vgpu_default_mmio_read(vgpu, offset, p_data, in failsafe_emulate_mmio_rw()
84 intel_vgpu_default_mmio_write(vgpu, offset, p_data, in failsafe_emulate_mmio_rw()
86 } else if (reg_is_gtt(gvt, offset)) { in failsafe_emulate_mmio_rw()
87 offset -= gvt->device_info.gtt_start_offset; in failsafe_emulate_mmio_rw()
88 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset; in failsafe_emulate_mmio_rw()
95 mutex_unlock(&vgpu->vgpu_lock); in failsafe_emulate_mmio_rw()
99 * intel_vgpu_emulate_mmio_read - emulate MMIO read
111 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_emulate_mmio_read()
112 struct drm_i915_private *i915 = gvt->gt->i915; in intel_vgpu_emulate_mmio_read()
113 unsigned int offset = 0; in intel_vgpu_emulate_mmio_read() local
114 int ret = -EINVAL; in intel_vgpu_emulate_mmio_read()
116 if (vgpu->failsafe) { in intel_vgpu_emulate_mmio_read()
120 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_mmio_read()
122 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); in intel_vgpu_emulate_mmio_read()
124 if (drm_WARN_ON(&i915->drm, bytes > 8)) in intel_vgpu_emulate_mmio_read()
127 if (reg_is_gtt(gvt, offset)) { in intel_vgpu_emulate_mmio_read()
128 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && in intel_vgpu_emulate_mmio_read()
129 !IS_ALIGNED(offset, 8))) in intel_vgpu_emulate_mmio_read()
131 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) in intel_vgpu_emulate_mmio_read()
133 if (drm_WARN_ON(&i915->drm, in intel_vgpu_emulate_mmio_read()
134 !reg_is_gtt(gvt, offset + bytes - 1))) in intel_vgpu_emulate_mmio_read()
137 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset, in intel_vgpu_emulate_mmio_read()
144 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { in intel_vgpu_emulate_mmio_read()
149 if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1))) in intel_vgpu_emulate_mmio_read()
152 if (!intel_gvt_mmio_is_unalign(gvt, offset)) { in intel_vgpu_emulate_mmio_read()
153 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes))) in intel_vgpu_emulate_mmio_read()
157 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true); in intel_vgpu_emulate_mmio_read()
161 intel_gvt_mmio_set_accessed(gvt, offset); in intel_vgpu_emulate_mmio_read()
167 offset, bytes); in intel_vgpu_emulate_mmio_read()
169 mutex_unlock(&vgpu->vgpu_lock); in intel_vgpu_emulate_mmio_read()
174 * intel_vgpu_emulate_mmio_write - emulate MMIO write
186 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_emulate_mmio_write()
187 struct drm_i915_private *i915 = gvt->gt->i915; in intel_vgpu_emulate_mmio_write()
188 unsigned int offset = 0; in intel_vgpu_emulate_mmio_write() local
189 int ret = -EINVAL; in intel_vgpu_emulate_mmio_write()
191 if (vgpu->failsafe) { in intel_vgpu_emulate_mmio_write()
196 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_mmio_write()
198 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); in intel_vgpu_emulate_mmio_write()
200 if (drm_WARN_ON(&i915->drm, bytes > 8)) in intel_vgpu_emulate_mmio_write()
203 if (reg_is_gtt(gvt, offset)) { in intel_vgpu_emulate_mmio_write()
204 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && in intel_vgpu_emulate_mmio_write()
205 !IS_ALIGNED(offset, 8))) in intel_vgpu_emulate_mmio_write()
207 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) in intel_vgpu_emulate_mmio_write()
209 if (drm_WARN_ON(&i915->drm, in intel_vgpu_emulate_mmio_write()
210 !reg_is_gtt(gvt, offset + bytes - 1))) in intel_vgpu_emulate_mmio_write()
213 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset, in intel_vgpu_emulate_mmio_write()
220 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { in intel_vgpu_emulate_mmio_write()
225 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false); in intel_vgpu_emulate_mmio_write()
229 intel_gvt_mmio_set_accessed(gvt, offset); in intel_vgpu_emulate_mmio_write()
233 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, in intel_vgpu_emulate_mmio_write()
236 mutex_unlock(&vgpu->vgpu_lock); in intel_vgpu_emulate_mmio_write()
242 * intel_vgpu_reset_mmio - reset virtual MMIO space
248 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reset_mmio()
249 const struct intel_gvt_device_info *info = &gvt->device_info; in intel_vgpu_reset_mmio()
250 void *mmio = gvt->firmware.mmio; in intel_vgpu_reset_mmio()
253 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size); in intel_vgpu_reset_mmio()
257 /* set the bit 0:2(Core C-State ) to C0 */ in intel_vgpu_reset_mmio()
263 if (IS_BROXTON(vgpu->gvt->gt->i915)) { in intel_vgpu_reset_mmio()
301 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET); in intel_vgpu_reset_mmio()
307 * intel_vgpu_init_mmio - init MMIO space
315 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; in intel_vgpu_init_mmio()
317 vgpu->mmio.vreg = vzalloc(info->mmio_size); in intel_vgpu_init_mmio()
318 if (!vgpu->mmio.vreg) in intel_vgpu_init_mmio()
319 return -ENOMEM; in intel_vgpu_init_mmio()
327 * intel_vgpu_clean_mmio - clean MMIO space
333 vfree(vgpu->mmio.vreg); in intel_vgpu_clean_mmio()
334 vgpu->mmio.vreg = NULL; in intel_vgpu_clean_mmio()