Lines Matching full:bytes
67 void *p_data, unsigned int bytes, bool read) in failsafe_emulate_mmio_rw() argument
82 bytes); in failsafe_emulate_mmio_rw()
85 bytes); in failsafe_emulate_mmio_rw()
90 memcpy(p_data, pt, bytes); in failsafe_emulate_mmio_rw()
92 memcpy(pt, p_data, bytes); in failsafe_emulate_mmio_rw()
103 * @bytes: access data length
109 void *p_data, unsigned int bytes) in intel_vgpu_emulate_mmio_read() argument
117 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true); in intel_vgpu_emulate_mmio_read()
124 if (drm_WARN_ON(&i915->drm, bytes > 8)) in intel_vgpu_emulate_mmio_read()
131 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) in intel_vgpu_emulate_mmio_read()
134 !reg_is_gtt(gvt, offset + bytes - 1))) in intel_vgpu_emulate_mmio_read()
138 p_data, bytes); in intel_vgpu_emulate_mmio_read()
145 ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes); in intel_vgpu_emulate_mmio_read()
149 if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1))) in intel_vgpu_emulate_mmio_read()
153 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes))) in intel_vgpu_emulate_mmio_read()
157 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true); in intel_vgpu_emulate_mmio_read()
167 offset, bytes); in intel_vgpu_emulate_mmio_read()
178 * @bytes: access data length
184 void *p_data, unsigned int bytes) in intel_vgpu_emulate_mmio_write() argument
192 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false); in intel_vgpu_emulate_mmio_write()
200 if (drm_WARN_ON(&i915->drm, bytes > 8)) in intel_vgpu_emulate_mmio_write()
207 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) in intel_vgpu_emulate_mmio_write()
210 !reg_is_gtt(gvt, offset + bytes - 1))) in intel_vgpu_emulate_mmio_write()
214 p_data, bytes); in intel_vgpu_emulate_mmio_write()
221 ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes); in intel_vgpu_emulate_mmio_write()
225 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false); in intel_vgpu_emulate_mmio_write()
234 bytes); in intel_vgpu_emulate_mmio_write()