Lines Matching +full:pch +full:- +full:msi +full:- +full:1
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
61 #define iir_to_regbase(iir) (iir - 0x8)
62 #define ier_to_regbase(ier) (ier - 0xC)
64 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
65 #define get_irq_info(irq, e) (irq->events[e].info)
169 struct intel_gvt_irq *irq = &gvt->irq; in regbase_to_irq_info()
172 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { in regbase_to_irq_info()
173 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
174 return irq->info[i]; in regbase_to_irq_info()
181 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
197 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_imr_handler()
198 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_imr_handler()
201 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_imr_handler()
206 ops->check_pending_irq(vgpu); in intel_vgpu_reg_imr_handler()
212 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
227 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_master_irq_handler()
228 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_master_irq_handler()
232 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier, in intel_vgpu_reg_master_irq_handler()
245 ops->check_pending_irq(vgpu); in intel_vgpu_reg_master_irq_handler()
251 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
266 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_ier_handler()
267 struct drm_i915_private *i915 = gvt->gt->i915; in intel_vgpu_reg_ier_handler()
268 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_ier_handler()
272 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_ier_handler()
278 if (drm_WARN_ON(&i915->drm, !info)) in intel_vgpu_reg_ier_handler()
279 return -EINVAL; in intel_vgpu_reg_ier_handler()
281 if (info->has_upstream_irq) in intel_vgpu_reg_ier_handler()
284 ops->check_pending_irq(vgpu); in intel_vgpu_reg_ier_handler()
290 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
305 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_reg_iir_handler()
306 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, in intel_vgpu_reg_iir_handler()
310 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_iir_handler()
313 if (drm_WARN_ON(&i915->drm, !info)) in intel_vgpu_reg_iir_handler()
314 return -EINVAL; in intel_vgpu_reg_iir_handler()
318 if (info->has_upstream_irq) in intel_vgpu_reg_iir_handler()
325 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
337 { -1, -1, ~0 },
343 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in update_upstream_irq()
344 struct intel_gvt_irq *irq = &vgpu->gvt->irq; in update_upstream_irq()
345 struct intel_gvt_irq_map *map = irq->irq_map; in update_upstream_irq()
351 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
353 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
355 if (!info->has_upstream_irq) in update_upstream_irq()
358 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { in update_upstream_irq()
359 if (info->group != map->down_irq_group) in update_upstream_irq()
363 up_irq_info = irq->info[map->up_irq_group]; in update_upstream_irq()
365 drm_WARN_ON(&i915->drm, up_irq_info != in update_upstream_irq()
366 irq->info[map->up_irq_group]); in update_upstream_irq()
368 bit = map->up_irq_bit; in update_upstream_irq()
370 if (val & map->down_irq_bitmask) in update_upstream_irq()
371 set_bits |= (1 << bit); in update_upstream_irq()
373 clear_bits |= (1 << bit); in update_upstream_irq()
376 if (drm_WARN_ON(&i915->drm, !up_irq_info)) in update_upstream_irq()
379 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { in update_upstream_irq()
380 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
386 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
388 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
393 if (up_irq_info->has_upstream_irq) in update_upstream_irq()
403 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { in init_irq_map()
404 up_info = irq->info[map->up_irq_group]; in init_irq_map()
405 up_bit = map->up_irq_bit; in init_irq_map()
406 down_info = irq->info[map->down_irq_group]; in init_irq_map()
408 set_bit(up_bit, up_info->downstream_irq_bitmap); in init_irq_map()
409 down_info->has_upstream_irq = true; in init_irq_map()
411 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", in init_irq_map()
412 up_info->group, up_bit, in init_irq_map()
413 down_info->group, map->down_irq_bitmask); in init_irq_map()
426 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset; in inject_virtual_interrupt()
434 /* Do not generate MSI if MSIEN is disabled */ in inject_virtual_interrupt()
438 if (WARN(control & GENMASK(15, 1), "only support one MSI format\n")) in inject_virtual_interrupt()
441 trace_inject_msi(vgpu->id, addr, data); in inject_virtual_interrupt()
448 * vblank interrupt request. But msi_trigger is null until msi is in inject_virtual_interrupt()
452 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) in inject_virtual_interrupt()
454 if (vgpu->msi_trigger) in inject_virtual_interrupt()
455 eventfd_signal(vgpu->msi_trigger); in inject_virtual_interrupt()
469 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
470 bit = irq->events[event].bit; in propagate_event()
474 trace_propagate_event(vgpu->id, irq_name[event], bit); in propagate_event()
484 if (!vgpu->irq.irq_warn_once[event]) { in handle_default_event_virt()
486 vgpu->id, event, irq_name[event]); in handle_default_event_virt()
487 vgpu->irq.irq_warn_once[event] = true; in handle_default_event_virt()
497 .name = #regname"-IRQ", \
499 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
504 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
516 .name = "PCH-IRQ",
518 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
524 struct intel_gvt_irq *irq = &vgpu->gvt->irq; in gen8_check_pending_irq()
531 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { in gen8_check_pending_irq()
532 struct intel_gvt_irq_info *info = irq->info[i]; in gen8_check_pending_irq()
535 if (!info->has_upstream_irq) in gen8_check_pending_irq()
538 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
556 s->events[e].bit = b; \ in gen8_init_irq()
557 s->events[e].info = s->info[i]; \ in gen8_init_irq()
558 s->info[i]->bit_to_event[b] = e;\ in gen8_init_irq()
563 s->info[g] = i; \ in gen8_init_irq()
564 (i)->group = g; \ in gen8_init_irq()
565 set_bit(g, s->irq_info_bitmap); \ in gen8_init_irq()
597 if (HAS_ENGINE(gvt->gt, VCS1)) { in gen8_init_irq()
622 /* PCH events */ in gen8_init_irq()
629 if (IS_BROADWELL(gvt->gt->i915)) { in gen8_init_irq()
642 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) { in gen8_init_irq()
667 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
679 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_trigger_virtual_event()
680 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_trigger_virtual_event()
681 struct intel_gvt_irq *irq = &gvt->irq; in intel_vgpu_trigger_virtual_event()
683 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_trigger_virtual_event()
686 drm_WARN_ON(&i915->drm, !handler); in intel_vgpu_trigger_virtual_event()
690 ops->check_pending_irq(vgpu); in intel_vgpu_trigger_virtual_event()
699 irq->events[i].info = NULL; in init_events()
700 irq->events[i].v_handler = handle_default_event_virt; in init_events()
705 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
708 * This function is called at driver loading stage, to initialize the GVT-g IRQ
716 struct intel_gvt_irq *irq = &gvt->irq; in intel_gvt_init_irq()
720 irq->ops = &gen8_irq_ops; in intel_gvt_init_irq()
721 irq->irq_map = gen8_irq_map; in intel_gvt_init_irq()
727 irq->ops->init_irq(irq); in intel_gvt_init_irq()