94 	void *p_data, unsigned int bytes)  in read_vreg()  argument
96 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);  in read_vreg()
100 	void *p_data, unsigned int bytes)  in write_vreg()  argument
102 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);  in write_vreg()
199 		unsigned int fence_num, void *p_data, unsigned int bytes)  in sanitize_fence_mmio_access()  argument
215 		memset(p_data, 0, bytes);  in sanitize_fence_mmio_access()
222 		unsigned int offset, void *p_data, unsigned int bytes)  in gamw_echo_dev_rw_ia_write()  argument
224 	u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;  in gamw_echo_dev_rw_ia_write()
242 	write_vreg(vgpu, offset, p_data, bytes);  in gamw_echo_dev_rw_ia_write()
247 		void *p_data, unsigned int bytes)  in fence_mmio_read()  argument
252 			p_data, bytes);  in fence_mmio_read()
255 	read_vreg(vgpu, off, p_data, bytes);  in fence_mmio_read()
260 		void *p_data, unsigned int bytes)  in fence_mmio_write()  argument
266 	ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);  in fence_mmio_write()
269 	write_vreg(vgpu, off, p_data, bytes);  in fence_mmio_write()
284 		unsigned int offset, void *p_data, unsigned int bytes)  in mul_force_wake_write()  argument
290 	new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);  in mul_force_wake_write()
318 			    void *p_data, unsigned int bytes)  in gdrst_mmio_write()  argument
323 	write_vreg(vgpu, offset, p_data, bytes);  in gdrst_mmio_write()
367 		void *p_data, unsigned int bytes)  in gmbus_mmio_read()  argument
369 	return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);  in gmbus_mmio_read()
373 		void *p_data, unsigned int bytes)  in gmbus_mmio_write()  argument
375 	return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);  in gmbus_mmio_write()
379 		unsigned int offset, void *p_data, unsigned int bytes)  in pch_pp_control_mmio_write()  argument
381 	write_vreg(vgpu, offset, p_data, bytes);  in pch_pp_control_mmio_write()
397 		unsigned int offset, void *p_data, unsigned int bytes)  in transconf_mmio_write()  argument
399 	write_vreg(vgpu, offset, p_data, bytes);  in transconf_mmio_write()
409 		void *p_data, unsigned int bytes)  in lcpll_ctl_mmio_write()  argument
411 	write_vreg(vgpu, offset, p_data, bytes);  in lcpll_ctl_mmio_write()
427 		void *p_data, unsigned int bytes)  in dpy_reg_mmio_read()  argument
446 	read_vreg(vgpu, offset, p_data, bytes);  in dpy_reg_mmio_read()
704 		void *p_data, unsigned int bytes)  in pipeconf_mmio_write()  argument
708 	write_vreg(vgpu, offset, p_data, bytes);  in pipeconf_mmio_write()
777 	unsigned int offset, void *p_data, unsigned int bytes)  in force_nonpriv_write()  argument
779 	u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);  in force_nonpriv_write()
794 		intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);  in force_nonpriv_write()
800 		void *p_data, unsigned int bytes)  in ddi_buf_ctl_mmio_write()  argument
802 	write_vreg(vgpu, offset, p_data, bytes);  in ddi_buf_ctl_mmio_write()
816 		unsigned int offset, void *p_data, unsigned int bytes)  in fdi_rx_iir_mmio_write()  argument
818 	vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;  in fdi_rx_iir_mmio_write()
908 		unsigned int offset, void *p_data, unsigned int bytes)  in update_fdi_rx_iir_status()  argument
925 	write_vreg(vgpu, offset, p_data, bytes);  in update_fdi_rx_iir_status()
952 		void *p_data, unsigned int bytes)  in dp_tp_ctl_mmio_write()  argument
958 	write_vreg(vgpu, offset, p_data, bytes);  in dp_tp_ctl_mmio_write()
970 		unsigned int offset, void *p_data, unsigned int bytes)  in dp_tp_status_mmio_write()  argument
975 	reg_val = *((u32 *)p_data);  in dp_tp_status_mmio_write()
985 		unsigned int offset, void *p_data, unsigned int bytes)  in pch_adpa_mmio_write()  argument
989 	write_vreg(vgpu, offset, p_data, bytes);  in pch_adpa_mmio_write()
998 		unsigned int offset, void *p_data, unsigned int bytes)  in south_chicken2_mmio_write()  argument
1002 	write_vreg(vgpu, offset, p_data, bytes);  in south_chicken2_mmio_write()
1016 		void *p_data, unsigned int bytes)  in pri_surf_mmio_write()  argument
1022 	write_vreg(vgpu, offset, p_data, bytes);  in pri_surf_mmio_write()
1039 		void *p_data, unsigned int bytes)  in spr_surf_mmio_write()  argument
1044 	write_vreg(vgpu, offset, p_data, bytes);  in spr_surf_mmio_write()
1056 			       unsigned int offset, void *p_data,  in reg50080_mmio_write()  argument
1064 	write_vreg(vgpu, offset, p_data, bytes);  in reg50080_mmio_write()
1164 		unsigned int offset, void *p_data, unsigned int bytes)  in dp_aux_ch_ctl_mmio_write()  argument
1178 	write_vreg(vgpu, offset, p_data, bytes);  in dp_aux_ch_ctl_mmio_write()
1328 	intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);  in dp_aux_ch_ctl_mmio_write()
1336 		void *p_data, unsigned int bytes)  in mbctl_write()  argument
1338 	*(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);  in mbctl_write()
1339 	write_vreg(vgpu, offset, p_data, bytes);  in mbctl_write()
1344 		void *p_data, unsigned int bytes)  in vga_control_mmio_write()  argument
1348 	write_vreg(vgpu, offset, p_data, bytes);  in vga_control_mmio_write()
1398 		void *p_data, unsigned int bytes)  in sbi_data_mmio_read()  argument
1407 	read_vreg(vgpu, offset, p_data, bytes);  in sbi_data_mmio_read()
1412 		void *p_data, unsigned int bytes)  in sbi_ctl_mmio_write()  argument
1416 	write_vreg(vgpu, offset, p_data, bytes);  in sbi_ctl_mmio_write()
1442 		void *p_data, unsigned int bytes)  in pvinfo_mmio_read()  argument
1446 	read_vreg(vgpu, offset, p_data, bytes);  in pvinfo_mmio_read()
1468 				offset, bytes, *(u32 *)p_data);  in pvinfo_mmio_read()
1518 		void *p_data, unsigned int bytes)  in pvinfo_mmio_write()  argument
1520 	u32 data = *(u32 *)p_data;  in pvinfo_mmio_write()
1556 		write_vreg(vgpu, offset, p_data, bytes);  in pvinfo_mmio_write()
1562 		unsigned int offset, void *p_data, unsigned int bytes)  in pf_write()  argument
1565 	u32 val = *(u32 *)p_data;  in pf_write()
1576 	return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);  in pf_write()
1580 		unsigned int offset, void *p_data, unsigned int bytes)  in power_well_ctl_mmio_write()  argument
1582 	write_vreg(vgpu, offset, p_data, bytes);  in power_well_ctl_mmio_write()
1595 		unsigned int offset, void *p_data, unsigned int bytes)  in gen9_dbuf_ctl_mmio_write()  argument
1597 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_dbuf_ctl_mmio_write()
1608 	unsigned int offset, void *p_data, unsigned int bytes)  in fpga_dbg_mmio_write()  argument
1610 	write_vreg(vgpu, offset, p_data, bytes);  in fpga_dbg_mmio_write()
1618 		void *p_data, unsigned int bytes)  in dma_ctrl_write()  argument
1623 	write_vreg(vgpu, offset, p_data, bytes);  in dma_ctrl_write()
1637 		void *p_data, unsigned int bytes)  in gen9_trtte_write()  argument
1640 	u32 trtte = *(u32 *)p_data;  in gen9_trtte_write()
1648 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_trtte_write()
1654 		void *p_data, unsigned int bytes)  in gen9_trtt_chicken_write()  argument
1656 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_trtt_chicken_write()
1661 		void *p_data, unsigned int bytes)  in dpll_status_read()  argument
1679 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);  in dpll_status_read()
1683 		void *p_data, unsigned int bytes)  in mailbox_write()  argument
1685 	u32 value = *(u32 *)p_data;  in mailbox_write()
1741 		void *p_data, unsigned int bytes)  in hws_pga_write()  argument
1743 	u32 value = *(u32 *)p_data;  in hws_pga_write()
1772 		unsigned int offset, void *p_data, unsigned int bytes)  in skl_power_well_ctl_write()  argument
1774 	u32 v = *(u32 *)p_data;  in skl_power_well_ctl_write()
1787 		void *p_data, unsigned int bytes)  in skl_lcpll_write()  argument
1789 	u32 v = *(u32 *)p_data;  in skl_lcpll_write()
1801 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_de_pll_enable_write()  argument
1803 	u32 v = *(u32 *)p_data;  in bxt_de_pll_enable_write()
1814 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_port_pll_enable_write()  argument
1816 	u32 v = *(u32 *)p_data;  in bxt_port_pll_enable_write()
1827 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_phy_ctl_family_write()  argument
1829 	u32 v = *(u32 *)p_data;  in bxt_phy_ctl_family_write()
1848 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_port_tx_dw3_read()  argument
1856 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);  in bxt_port_tx_dw3_read()
1860 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_pcs_dw12_grp_write()  argument
1862 	u32 v = *(u32 *)p_data;  in bxt_pcs_dw12_grp_write()
1878 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_gt_disp_pwron_write()  argument
1880 	u32 v = *(u32 *)p_data;  in bxt_gt_disp_pwron_write()
1903 		unsigned int offset, void *p_data, unsigned int bytes)  in edp_psr_imr_iir_write()  argument
1920 			      void *p_data, unsigned int bytes)  in bxt_ppat_low_write()  argument
1938 			   unsigned int offset, void *p_data,  in guc_status_read()  argument
1942 	read_vreg(vgpu, offset, p_data, bytes);  in guc_status_read()
1948 		unsigned int offset, void *p_data, unsigned int bytes)  in mmio_read_from_hw()  argument
1971 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);  in mmio_read_from_hw()
1975 		void *p_data, unsigned int bytes)  in elsp_mmio_write()  argument
1980 	u32 data = *(u32 *)p_data;  in elsp_mmio_write()
2017 		void *p_data, unsigned int bytes)  in ring_mode_mmio_write()  argument
2019 	u32 data = *(u32 *)p_data;  in ring_mode_mmio_write()
2025 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);  in ring_mode_mmio_write()
2028 		(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);  in ring_mode_mmio_write()
2029 	write_vreg(vgpu, offset, p_data, bytes);  in ring_mode_mmio_write()
2076 		unsigned int offset, void *p_data, unsigned int bytes)  in gvt_reg_tlb_control_handler()  argument
2080 	write_vreg(vgpu, offset, p_data, bytes);  in gvt_reg_tlb_control_handler()
2108 	unsigned int offset, void *p_data, unsigned int bytes)  in ring_reset_ctl_write()  argument
2112 	write_vreg(vgpu, offset, p_data, bytes);  in ring_reset_ctl_write()
2125 				    unsigned int offset, void *p_data,  in csfe_chicken1_mmio_write()  argument
2128 	u32 data = *(u32 *)p_data;  in csfe_chicken1_mmio_write()
2130 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);  in csfe_chicken1_mmio_write()
2131 	write_vreg(vgpu, offset, p_data, bytes);  in csfe_chicken1_mmio_write()
3060 		void *p_data, unsigned int bytes)  in intel_vgpu_default_mmio_read()  argument
3062 	read_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_default_mmio_read()
3077 		void *p_data, unsigned int bytes)  in intel_vgpu_default_mmio_write()  argument
3079 	write_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_default_mmio_write()
3094 		void *p_data, unsigned int bytes)  in intel_vgpu_mask_mmio_write()  argument
3099 	write_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_mask_mmio_write()