2147 #define MMIO_DH(reg, d, r, w) \  macro
2198 	MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,  in init_generic_mmio_info()
2216 	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);  in init_generic_mmio_info()
2274 	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL,  in init_generic_mmio_info()
2276 	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL,  in init_generic_mmio_info()
2278 	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL,  in init_generic_mmio_info()
2280 	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL,  in init_generic_mmio_info()
2282 	MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);  in init_generic_mmio_info()
2283 	MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,  in init_generic_mmio_info()
2285 	MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);  in init_generic_mmio_info()
2286 	MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,  in init_generic_mmio_info()
2288 	MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);  in init_generic_mmio_info()
2289 	MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,  in init_generic_mmio_info()
2291 	MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);  in init_generic_mmio_info()
2292 	MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,  in init_generic_mmio_info()
2294 	MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);  in init_generic_mmio_info()
2295 	MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,  in init_generic_mmio_info()
2297 	MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);  in init_generic_mmio_info()
2298 	MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,  in init_generic_mmio_info()
2312 	MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);  in init_generic_mmio_info()
2314 	MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);  in init_generic_mmio_info()
2315 	MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);  in init_generic_mmio_info()
2317 	MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);  in init_generic_mmio_info()
2318 	MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);  in init_generic_mmio_info()
2319 	MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);  in init_generic_mmio_info()
2320 	MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);  in init_generic_mmio_info()
2321 	MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);  in init_generic_mmio_info()
2322 	MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);  in init_generic_mmio_info()
2323 	MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);  in init_generic_mmio_info()
2324 	MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);  in init_generic_mmio_info()
2325 	MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);  in init_generic_mmio_info()
2326 	MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);  in init_generic_mmio_info()
2327 	MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);  in init_generic_mmio_info()
2328 	MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);  in init_generic_mmio_info()
2329 	MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);  in init_generic_mmio_info()
2330 	MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);  in init_generic_mmio_info()
2331 	MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);  in init_generic_mmio_info()
2332 	MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);  in init_generic_mmio_info()
2341 	MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);  in init_generic_mmio_info()
2342 	MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);  in init_generic_mmio_info()
2343 	MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);  in init_generic_mmio_info()
2344 	MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);  in init_generic_mmio_info()
2345 	MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);  in init_generic_mmio_info()
2350 	MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);  in init_generic_mmio_info()
2351 	MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);  in init_generic_mmio_info()
2352 	MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);  in init_generic_mmio_info()
2353 	MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);  in init_generic_mmio_info()
2354 	MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);  in init_generic_mmio_info()
2356 	MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);  in init_generic_mmio_info()
2357 	MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);  in init_generic_mmio_info()
2358 	MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);  in init_generic_mmio_info()
2359 	MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);  in init_generic_mmio_info()
2360 	MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);  in init_generic_mmio_info()
2362 	MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);  in init_generic_mmio_info()
2363 	MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);  in init_generic_mmio_info()
2364 	MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);  in init_generic_mmio_info()
2365 	MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);  in init_generic_mmio_info()
2366 	MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);  in init_generic_mmio_info()
2368 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);  in init_generic_mmio_info()
2369 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);  in init_generic_mmio_info()
2370 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);  in init_generic_mmio_info()
2371 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);  in init_generic_mmio_info()
2373 	MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);  in init_generic_mmio_info()
2376 	MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);  in init_generic_mmio_info()
2377 	MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);  in init_generic_mmio_info()
2378 	MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);  in init_generic_mmio_info()
2379 	MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);  in init_generic_mmio_info()
2380 	MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);  in init_generic_mmio_info()
2381 	MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);  in init_generic_mmio_info()
2382 	MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);  in init_generic_mmio_info()
2383 	MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);  in init_generic_mmio_info()
2384 	MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);  in init_generic_mmio_info()
2385 	MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);  in init_generic_mmio_info()
2387 	MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);  in init_generic_mmio_info()
2389 	MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);  in init_generic_mmio_info()
2391 	MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);  in init_generic_mmio_info()
2392 	MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);  in init_generic_mmio_info()
2394 	MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);  in init_generic_mmio_info()
2397 	MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);  in init_generic_mmio_info()
2424 	MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);  in init_generic_mmio_info()
2425 	MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);  in init_generic_mmio_info()
2426 	MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);  in init_generic_mmio_info()
2427 	MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);  in init_generic_mmio_info()
2428 	MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);  in init_generic_mmio_info()
2443 	MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);  in init_generic_mmio_info()
2444 	MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);  in init_generic_mmio_info()
2445 	MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);  in init_generic_mmio_info()
2454 	MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);  in init_bdw_mmio_info()
2455 	MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);  in init_bdw_mmio_info()
2456 	MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);  in init_bdw_mmio_info()
2458 	MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);  in init_bdw_mmio_info()
2459 	MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);  in init_bdw_mmio_info()
2460 	MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);  in init_bdw_mmio_info()
2462 	MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);  in init_bdw_mmio_info()
2463 	MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);  in init_bdw_mmio_info()
2464 	MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);  in init_bdw_mmio_info()
2466 	MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);  in init_bdw_mmio_info()
2467 	MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);  in init_bdw_mmio_info()
2468 	MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);  in init_bdw_mmio_info()
2470 	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2472 	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2474 	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2477 	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2479 	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2481 	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2484 	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2486 	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2488 	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2491 	MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);  in init_bdw_mmio_info()
2492 	MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);  in init_bdw_mmio_info()
2493 	MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);  in init_bdw_mmio_info()
2495 	MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);  in init_bdw_mmio_info()
2496 	MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);  in init_bdw_mmio_info()
2497 	MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);  in init_bdw_mmio_info()
2499 	MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);  in init_bdw_mmio_info()
2500 	MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);  in init_bdw_mmio_info()
2501 	MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);  in init_bdw_mmio_info()
2503 	MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,  in init_bdw_mmio_info()
2536 	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);  in init_bdw_mmio_info()
2589 	MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);  in init_skl_mmio_info()
2590 	MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2591 	MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);  in init_skl_mmio_info()
2592 	MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2593 	MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);  in init_skl_mmio_info()
2594 	MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2603 	MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);  in init_skl_mmio_info()
2605 	MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);  in init_skl_mmio_info()
2609 	MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2610 	MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);  in init_skl_mmio_info()
2611 	MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);  in init_skl_mmio_info()
2612 	MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);  in init_skl_mmio_info()
2614 	MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2615 	MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2616 	MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2617 	MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2618 	MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2619 	MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2621 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2622 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2623 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2624 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2625 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2626 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2628 	MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2629 	MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2630 	MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2631 	MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2632 	MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2633 	MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);  in init_skl_mmio_info()
2635 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2636 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2637 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2638 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2640 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2641 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2642 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2643 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2645 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2646 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2647 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2648 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2650 	MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2651 	MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2652 	MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2654 	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2655 	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2656 	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2658 	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2659 	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2660 	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2662 	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2663 	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2664 	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2666 	MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2667 	MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2668 	MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2670 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2671 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2672 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2673 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2675 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2676 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2677 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2678 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2680 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2681 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2682 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2683 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2685 	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2686 	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2687 	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2688 	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2690 	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2691 	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2692 	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2693 	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2695 	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2696 	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2697 	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2698 	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2700 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2701 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2702 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2703 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2705 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2706 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2707 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2708 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2710 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2711 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2712 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2713 	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);  in init_skl_mmio_info()
2739 	MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);  in init_skl_mmio_info()
2760 	MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);  in init_bxt_mmio_info()
2761 	MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,  in init_bxt_mmio_info()
2763 	MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,  in init_bxt_mmio_info()
2765 	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,  in init_bxt_mmio_info()
2767 	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,  in init_bxt_mmio_info()
2769 	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,  in init_bxt_mmio_info()
2772 	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,  in init_bxt_mmio_info()
2774 	MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,  in init_bxt_mmio_info()
2776 	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,  in init_bxt_mmio_info()
2778 	MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,  in init_bxt_mmio_info()
2780 	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,  in init_bxt_mmio_info()
2782 	MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,  in init_bxt_mmio_info()
2784 	MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);  in init_bxt_mmio_info()
2799 	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);  in init_bxt_mmio_info()