Lines Matching refs:D_BXT
80 return D_BXT; in intel_gvt_get_device_type()
2760 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); in init_bxt_mmio_info()
2761 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, in init_bxt_mmio_info()
2763 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, in init_bxt_mmio_info()
2765 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, in init_bxt_mmio_info()
2767 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, in init_bxt_mmio_info()
2769 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, in init_bxt_mmio_info()
2772 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2774 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()
2776 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
2778 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT, in init_bxt_mmio_info()
2780 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2782 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()
2784 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); in init_bxt_mmio_info()
2785 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); in init_bxt_mmio_info()
2786 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); in init_bxt_mmio_info()
2787 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); in init_bxt_mmio_info()
2789 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2791 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2793 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2795 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2797 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); in init_bxt_mmio_info()
2799 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); in init_bxt_mmio_info()