2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
51 #include "edid.h"
65 /* Describe per-platform limitations. */
112 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
125 #define vgpu_opregion(vgpu) (&(vgpu->opregion))
243 	(((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
280 /* This reg is in GVT's mmio save-restor list and in hardware
311 	enum intel_vgpu_edid edid;  member
376 	/* per-vGPU vblank emulation request */
385 	set_bit(service, (void *)&gvt->service_request);  in intel_gvt_request_service()
386 	wake_up(&gvt->service_thread_wq);  in intel_gvt_request_service()
400 #define gvt_to_ggtt(gvt)	((gvt)->gt->ggtt)
403 #define gvt_aperture_sz(gvt)	  gvt_to_ggtt(gvt)->mappable_end
404 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
406 #define gvt_ggtt_gm_sz(gvt)	gvt_to_ggtt(gvt)->vm.total
407 #define gvt_ggtt_sz(gvt)	(gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
408 #define gvt_hidden_sz(gvt)	(gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
412 				     + gvt_aperture_sz(gvt) - 1)
417 				   + gvt_hidden_sz(gvt) - 1)
419 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
422 #define vgpu_aperture_offset(vgpu)	((vgpu)->gm.low_gm_node.start)
423 #define vgpu_hidden_offset(vgpu)	((vgpu)->gm.high_gm_node.start)
424 #define vgpu_aperture_sz(vgpu)		((vgpu)->gm.aperture_sz)
425 #define vgpu_hidden_sz(vgpu)		((vgpu)->gm.hidden_sz)
428 	(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
430 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
433 	(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
437 	(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
441 	(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
443 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)
458 	(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
460 	(*(u32 *)(vgpu->mmio.vreg + (offset)))
462 	(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
464 	(*(u64 *)(vgpu->mmio.vreg + (offset)))
467 	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
468 		for_each_if(test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
481 		 * only update bit 31 - bit 4,  in intel_vgpu_write_pci_bar()
482 		 * leave the bit 3 - bit 0 unchanged.  in intel_vgpu_write_pci_bar()
556 	return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &  in intel_vgpu_get_bar_gpa()
579 	intel_runtime_pm_get(gt->uncore->rpm);  in mmio_hw_access_pre()
584 	intel_runtime_pm_put_unchecked(gt->uncore->rpm);  in mmio_hw_access_post()
588  * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
596 	gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;  in intel_gvt_mmio_set_accessed()
600  * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command
610 	return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;  in intel_gvt_mmio_is_cmd_accessible()
614  * intel_gvt_mmio_set_cmd_accessible -
623 	gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS;  in intel_gvt_mmio_set_cmd_accessible()
627  * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
635 	return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;  in intel_gvt_mmio_is_unalign()
639  * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
650 	return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;  in intel_gvt_mmio_has_mode_mask()
654  * intel_gvt_mmio_is_sr_in_ctx -
666 	return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;  in intel_gvt_mmio_is_sr_in_ctx()
670  * intel_gvt_mmio_set_sr_in_ctx -
671  *		mask an MMIO in GVT's mmio save-restore list and also
680 	gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;  in intel_gvt_mmio_set_sr_in_ctx()
685  * intel_gvt_mmio_set_cmd_write_patch -
695 	gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH;  in intel_gvt_mmio_set_cmd_write_patch()
699  * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to
710 	return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH;  in intel_gvt_mmio_is_cmd_write_patch()
714  * intel_gvt_read_gpa - copy data from GPA to host data buffer
726 	if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))  in intel_gvt_read_gpa()
727 		return -ESRCH;  in intel_gvt_read_gpa()
728 	return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false);  in intel_gvt_read_gpa()
732  * intel_gvt_write_gpa - copy data from host data buffer to GPA
744 	if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))  in intel_gvt_write_gpa()
745 		return -ESRCH;  in intel_gvt_write_gpa()
746 	return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true);  in intel_gvt_write_gpa()