2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
56 	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
57 	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
58 	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
59 	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
61 	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
62 	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
64 	/* non-supported format has bpp default to 0 */
69 	{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
70 	{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
71 	{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
72 	{DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
74 	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
75 	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
76 	{DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
77 	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
79 	{DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
80 	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
81 	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
82 	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
84 	/* non-supported format has bpp default to 0 */
143 			return -EINVAL;  in skl_format_to_drm()
156 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_get_stride()
175 			else if (bpp == 16 || bpp == 32 || bpp == 64)  in intel_vgpu_get_stride()
201  * intel_vgpu_decode_primary_plane - Decode primary plane
207  * 0 on success, non-zero if failed.
212 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_decode_primary_plane()
218 		return -ENODEV;  in intel_vgpu_decode_primary_plane()
221 	plane->enabled = !!(val & DISP_ENABLE);  in intel_vgpu_decode_primary_plane()
222 	if (!plane->enabled)  in intel_vgpu_decode_primary_plane()
223 		return -ENODEV;  in intel_vgpu_decode_primary_plane()
226 		plane->tiled = val & PLANE_CTL_TILED_MASK;  in intel_vgpu_decode_primary_plane()
234 			gvt_vgpu_err("Out-of-bounds pixel format index\n");  in intel_vgpu_decode_primary_plane()
235 			return -EINVAL;  in intel_vgpu_decode_primary_plane()
238 		plane->bpp = skl_pixel_formats[fmt].bpp;  in intel_vgpu_decode_primary_plane()
239 		plane->drm_format = skl_pixel_formats[fmt].drm_format;  in intel_vgpu_decode_primary_plane()
241 		plane->tiled = val & DISP_TILED;  in intel_vgpu_decode_primary_plane()
243 		plane->bpp = bdw_pixel_formats[fmt].bpp;  in intel_vgpu_decode_primary_plane()
244 		plane->drm_format = bdw_pixel_formats[fmt].drm_format;  in intel_vgpu_decode_primary_plane()
247 	if (!plane->bpp) {  in intel_vgpu_decode_primary_plane()
248 		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);  in intel_vgpu_decode_primary_plane()
249 		return -EINVAL;  in intel_vgpu_decode_primary_plane()
252 	plane->hw_format = fmt;  in intel_vgpu_decode_primary_plane()
254 	plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_primary_plane()
255 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_primary_plane()
256 		return  -EINVAL;  in intel_vgpu_decode_primary_plane()
258 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_primary_plane()
259 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {  in intel_vgpu_decode_primary_plane()
261 				plane->base);  in intel_vgpu_decode_primary_plane()
262 		return  -EINVAL;  in intel_vgpu_decode_primary_plane()
265 	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,  in intel_vgpu_decode_primary_plane()
268 		_PRI_PLANE_STRIDE_MASK, plane->bpp);  in intel_vgpu_decode_primary_plane()
270 	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >>  in intel_vgpu_decode_primary_plane()
272 	plane->width += 1;  in intel_vgpu_decode_primary_plane()
273 	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) &  in intel_vgpu_decode_primary_plane()
275 	plane->height += 1;	/* raw height is one minus the real value */  in intel_vgpu_decode_primary_plane()
278 	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>  in intel_vgpu_decode_primary_plane()
280 	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>  in intel_vgpu_decode_primary_plane()
296 	{DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
297 	{DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
298 	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
299 	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
301 	/* non-supported format has bpp default to 0 */
331  * intel_vgpu_decode_cursor_plane - Decode sprite plane
337  * 0 on success, non-zero if failed.
342 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_decode_cursor_plane()
349 		return -ENODEV;  in intel_vgpu_decode_cursor_plane()
353 	plane->enabled = (mode != MCURSOR_MODE_DISABLE);  in intel_vgpu_decode_cursor_plane()
354 	if (!plane->enabled)  in intel_vgpu_decode_cursor_plane()
355 		return -ENODEV;  in intel_vgpu_decode_cursor_plane()
360 		gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);  in intel_vgpu_decode_cursor_plane()
361 		return -EINVAL;  in intel_vgpu_decode_cursor_plane()
363 	plane->mode = mode;  in intel_vgpu_decode_cursor_plane()
364 	plane->bpp = cursor_pixel_formats[index].bpp;  in intel_vgpu_decode_cursor_plane()
365 	plane->drm_format = cursor_pixel_formats[index].drm_format;  in intel_vgpu_decode_cursor_plane()
366 	plane->width = cursor_pixel_formats[index].width;  in intel_vgpu_decode_cursor_plane()
367 	plane->height = cursor_pixel_formats[index].height;  in intel_vgpu_decode_cursor_plane()
377 	plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_cursor_plane()
378 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_cursor_plane()
379 		return  -EINVAL;  in intel_vgpu_decode_cursor_plane()
381 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_cursor_plane()
382 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {  in intel_vgpu_decode_cursor_plane()
384 				plane->base);  in intel_vgpu_decode_cursor_plane()
385 		return  -EINVAL;  in intel_vgpu_decode_cursor_plane()
389 	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;  in intel_vgpu_decode_cursor_plane()
390 	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;  in intel_vgpu_decode_cursor_plane()
391 	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;  in intel_vgpu_decode_cursor_plane()
392 	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;  in intel_vgpu_decode_cursor_plane()
394 	plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));  in intel_vgpu_decode_cursor_plane()
395 	plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));  in intel_vgpu_decode_cursor_plane()
402 	[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
403 	[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
404 	[0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
405 	[0x4] = {DRM_FORMAT_AYUV, 32,
406 		"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
410  * intel_vgpu_decode_sprite_plane - Decode sprite plane
416  * 0 on success, non-zero if failed.
428 		return -ENODEV;  in intel_vgpu_decode_sprite_plane()
431 	plane->enabled = !!(val & SPRITE_ENABLE);  in intel_vgpu_decode_sprite_plane()
432 	if (!plane->enabled)  in intel_vgpu_decode_sprite_plane()
433 		return -ENODEV;  in intel_vgpu_decode_sprite_plane()
435 	plane->tiled = !!(val & SPRITE_TILED);  in intel_vgpu_decode_sprite_plane()
442 		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);  in intel_vgpu_decode_sprite_plane()
443 		return -EINVAL;  in intel_vgpu_decode_sprite_plane()
445 	plane->hw_format = fmt;  in intel_vgpu_decode_sprite_plane()
446 	plane->bpp = sprite_pixel_formats[fmt].bpp;  in intel_vgpu_decode_sprite_plane()
479 	plane->drm_format = drm_format;  in intel_vgpu_decode_sprite_plane()
481 	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_sprite_plane()
482 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_sprite_plane()
483 		return  -EINVAL;  in intel_vgpu_decode_sprite_plane()
485 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_sprite_plane()
486 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {  in intel_vgpu_decode_sprite_plane()
488 				plane->base);  in intel_vgpu_decode_sprite_plane()
489 		return  -EINVAL;  in intel_vgpu_decode_sprite_plane()
492 	plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &  in intel_vgpu_decode_sprite_plane()
496 	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>  in intel_vgpu_decode_sprite_plane()
498 	plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>  in intel_vgpu_decode_sprite_plane()
500 	plane->height += 1;	/* raw height is one minus the real value */  in intel_vgpu_decode_sprite_plane()
501 	plane->width += 1;	/* raw width is one minus the real value */  in intel_vgpu_decode_sprite_plane()
504 	plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;  in intel_vgpu_decode_sprite_plane()
505 	plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;  in intel_vgpu_decode_sprite_plane()
508 	plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>  in intel_vgpu_decode_sprite_plane()
510 	plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>  in intel_vgpu_decode_sprite_plane()