2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
54 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;  in edid_get_byte()  local
57 	if (edid->state == I2C_NOT_SPECIFIED || !edid->target_selected) {  in edid_get_byte()
58 		gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");  in edid_get_byte()
61 	if (edid->current_edid_read >= EDID_SIZE) {  in edid_get_byte()
62 		gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");  in edid_get_byte()
66 	if (!edid->edid_available) {  in edid_get_byte()
67 		gvt_vgpu_err("Reading EDID but EDID is not available!\n");  in edid_get_byte()
71 	if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {  in edid_get_byte()
73 			intel_vgpu_port(vgpu, edid->port)->edid;  in edid_get_byte()
75 		chr = edid_data->edid_block[edid->current_edid_read];  in edid_get_byte()
76 		edid->current_edid_read++;  in edid_get_byte()
78 		gvt_vgpu_err("No EDID available during the reading?\n");  in edid_get_byte()
86 	int port = -EINVAL;  in cnp_get_port_from_gmbus0()
102 	int port = -EINVAL;  in bxt_get_port_from_gmbus0()
116 	int port = -EINVAL;  in get_port_from_gmbus0()
132 	if (!vgpu->display.i2c_edid.edid_available)  in reset_gmbus_controller()
134 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;  in reset_gmbus_controller()
141 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in gmbus0_mmio_write()
159 	if (drm_WARN_ON(&i915->drm, port < 0))  in gmbus0_mmio_write()
162 	vgpu->display.i2c_edid.state = I2C_GMBUS;  in gmbus0_mmio_write()
163 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus0_mmio_write()
170 		vgpu->display.i2c_edid.port = port;  in gmbus0_mmio_write()
171 		vgpu->display.i2c_edid.edid_available = true;  in gmbus0_mmio_write()
181 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in gmbus1_mmio_write()
211 		i2c_edid->gmbus.total_byte_count =  in gmbus1_mmio_write()
215 		/* vgpu gmbus only support EDID */  in gmbus1_mmio_write()
217 			i2c_edid->target_selected = true;  in gmbus1_mmio_write()
222 					vgpu->id, target_addr);  in gmbus1_mmio_write()
226 			i2c_edid->current_edid_read =  in gmbus1_mmio_write()
229 		i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);  in gmbus1_mmio_write()
245 				 * few milliseconds. In emulation, we just set  in gmbus1_mmio_write()
249 				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus1_mmio_write()
259 			 * START (-->INDEX) -->DATA  in gmbus1_mmio_write()
261 			i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;  in gmbus1_mmio_write()
282 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in gmbus3_mmio_write()
284 	drm_WARN_ON(&i915->drm, 1);  in gmbus3_mmio_write()
293 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in gmbus3_mmio_read()
294 	int byte_left = i2c_edid->gmbus.total_byte_count -  in gmbus3_mmio_read()
295 				i2c_edid->current_edid_read;  in gmbus3_mmio_read()
317 			switch (i2c_edid->gmbus.cycle_type) {  in gmbus3_mmio_read()
320 				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus3_mmio_read()
325 				i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;  in gmbus3_mmio_read()
359 	/* All other bits are read-only */  in gmbus2_mmio_write()
364  * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
379 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_gmbus_read()
381 	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))  in intel_gvt_i2c_handle_gmbus_read()
382 		return -EINVAL;  in intel_gvt_i2c_handle_gmbus_read()
394  * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
409 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_gmbus_write()
411 	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))  in intel_gvt_i2c_handle_gmbus_write()
412 		return -EINVAL;  in intel_gvt_i2c_handle_gmbus_write()
460 		reg = -1;  in get_aux_ch_reg()
467  * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
481 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_aux_ch_write()
482 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in intel_gvt_i2c_handle_aux_ch_write()
518 			i2c_edid->aux_ch.i2c_over_aux_ch = true;  in intel_gvt_i2c_handle_aux_ch_write()
519 			i2c_edid->aux_ch.aux_ch_mot = true;  in intel_gvt_i2c_handle_aux_ch_write()
524 				i2c_edid->state = I2C_AUX_CH;  in intel_gvt_i2c_handle_aux_ch_write()
525 				i2c_edid->port = port_idx;  in intel_gvt_i2c_handle_aux_ch_write()
526 				i2c_edid->target_selected = true;  in intel_gvt_i2c_handle_aux_ch_write()
530 					i2c_edid->edid_available = true;  in intel_gvt_i2c_handle_aux_ch_write()
535 		 * We only support EDID reading from I2C_over_AUX. And  in intel_gvt_i2c_handle_aux_ch_write()
538 		 * support the gfx driver to do EDID access.  in intel_gvt_i2c_handle_aux_ch_write()
541 		if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))  in intel_gvt_i2c_handle_aux_ch_write()
543 		if (drm_WARN_ON(&i915->drm, msg_length != 4))  in intel_gvt_i2c_handle_aux_ch_write()
545 		if (i2c_edid->edid_available && i2c_edid->target_selected) {  in intel_gvt_i2c_handle_aux_ch_write()
561  * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
564  * This function is used to initialize vGPU i2c edid emulation stuffs
569 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;  in intel_vgpu_init_i2c_edid()  local
571 	edid->state = I2C_NOT_SPECIFIED;  in intel_vgpu_init_i2c_edid()
573 	edid->port = -1;  in intel_vgpu_init_i2c_edid()
574 	edid->target_selected = false;  in intel_vgpu_init_i2c_edid()
575 	edid->edid_available = false;  in intel_vgpu_init_i2c_edid()
576 	edid->current_edid_read = 0;  in intel_vgpu_init_i2c_edid()
578 	memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));  in intel_vgpu_init_i2c_edid()
580 	edid->aux_ch.i2c_over_aux_ch = false;  in intel_vgpu_init_i2c_edid()
581 	edid->aux_ch.aux_ch_mot = false;  in intel_vgpu_init_i2c_edid()