Lines Matching full:vgpu
46 static int get_edp_pipe(struct intel_vgpu *vgpu) in get_edp_pipe() argument
48 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); in get_edp_pipe()
66 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) in edp_pipe_is_enabled() argument
68 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in edp_pipe_is_enabled()
70 if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled()
73 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) in edp_pipe_is_enabled()
78 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) in pipe_is_enabled() argument
80 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in pipe_is_enabled()
86 if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled()
89 if (edp_pipe_is_enabled(vgpu) && in pipe_is_enabled()
90 get_edp_pipe(vgpu) == pipe) in pipe_is_enabled()
178 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) in emulate_monitor_status_change() argument
180 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_monitor_status_change()
188 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in emulate_monitor_status_change()
194 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &= in emulate_monitor_status_change()
196 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
197 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
198 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
199 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
203 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &= in emulate_monitor_status_change()
207 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= in emulate_monitor_status_change()
212 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= in emulate_monitor_status_change()
214 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= in emulate_monitor_status_change()
218 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= in emulate_monitor_status_change()
223 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= in emulate_monitor_status_change()
226 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
228 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
230 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
232 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
234 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ in emulate_monitor_status_change()
235 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; in emulate_monitor_status_change()
236 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; in emulate_monitor_status_change()
238 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); in emulate_monitor_status_change()
239 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change()
241 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in emulate_monitor_status_change()
243 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change()
244 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); in emulate_monitor_status_change()
246 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
247 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
250 * Only 1 PIPE enabled in current vGPU display and PIPE_A is in emulate_monitor_status_change()
255 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
256 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; in emulate_monitor_status_change()
264 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); in emulate_monitor_status_change()
265 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
266 vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
267 vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
268 vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
271 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
272 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); in emulate_monitor_status_change()
273 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in emulate_monitor_status_change()
275 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= in emulate_monitor_status_change()
277 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in emulate_monitor_status_change()
279 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in emulate_monitor_status_change()
282 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= in emulate_monitor_status_change()
286 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
288 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
290 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
294 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
296 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
300 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in emulate_monitor_status_change()
301 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
302 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); in emulate_monitor_status_change()
303 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
305 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
307 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in emulate_monitor_status_change()
309 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in emulate_monitor_status_change()
312 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= in emulate_monitor_status_change()
316 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
318 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
320 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
325 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
327 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
331 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { in emulate_monitor_status_change()
332 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
333 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); in emulate_monitor_status_change()
334 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
336 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
338 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in emulate_monitor_status_change()
340 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in emulate_monitor_status_change()
343 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= in emulate_monitor_status_change()
347 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= in emulate_monitor_status_change()
349 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= in emulate_monitor_status_change()
351 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
356 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
358 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
365 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | in emulate_monitor_status_change()
373 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | in emulate_monitor_status_change()
375 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= in emulate_monitor_status_change()
381 * Only 1 PIPE enabled in current vGPU display and PIPE_A is in emulate_monitor_status_change()
388 vgpu_vreg_t(vgpu, DPLL_CTRL1) = in emulate_monitor_status_change()
390 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= in emulate_monitor_status_change()
392 vgpu_vreg_t(vgpu, LCPLL1_CTL) = in emulate_monitor_status_change()
394 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); in emulate_monitor_status_change()
401 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); in emulate_monitor_status_change()
402 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
403 vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
404 vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
405 vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
408 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in emulate_monitor_status_change()
409 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
411 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
413 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
415 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
416 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= in emulate_monitor_status_change()
419 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= in emulate_monitor_status_change()
424 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= in emulate_monitor_status_change()
426 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= in emulate_monitor_status_change()
429 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
430 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
431 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; in emulate_monitor_status_change()
434 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { in emulate_monitor_status_change()
435 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
437 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
439 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
441 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; in emulate_monitor_status_change()
442 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= in emulate_monitor_status_change()
445 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= in emulate_monitor_status_change()
450 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= in emulate_monitor_status_change()
452 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= in emulate_monitor_status_change()
455 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
456 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
457 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
460 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { in emulate_monitor_status_change()
461 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
463 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
465 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
467 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; in emulate_monitor_status_change()
468 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= in emulate_monitor_status_change()
471 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= in emulate_monitor_status_change()
476 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= in emulate_monitor_status_change()
478 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= in emulate_monitor_status_change()
481 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
482 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
483 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; in emulate_monitor_status_change()
490 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { in emulate_monitor_status_change()
491 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; in emulate_monitor_status_change()
494 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
496 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
499 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; in emulate_monitor_status_change()
501 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; in emulate_monitor_status_change()
506 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; in emulate_monitor_status_change()
510 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
511 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
512 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
513 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
516 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
519 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) in clean_virtual_dp_monitor() argument
521 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); in clean_virtual_dp_monitor()
533 struct intel_vgpu *vgpu; in vblank_timer_fn() local
536 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); in vblank_timer_fn()
538 /* Set vblank emulation request per-vGPU bit */ in vblank_timer_fn()
539 intel_gvt_request_service(vgpu->gvt, in vblank_timer_fn()
540 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); in vblank_timer_fn()
545 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, in setup_virtual_dp_monitor() argument
548 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in setup_virtual_dp_monitor()
549 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); in setup_virtual_dp_monitor()
550 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; in setup_virtual_dp_monitor()
575 vgpu->display.port_num = port_num; in setup_virtual_dp_monitor()
583 emulate_monitor_status_change(vgpu); in setup_virtual_dp_monitor()
589 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer
590 * @vgpu: vGPU operated
593 * This function is used to turn on/off or update the per-vGPU vblank_timer
598 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) in vgpu_update_vblank_emulation() argument
600 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; in vgpu_update_vblank_emulation()
602 intel_vgpu_port(vgpu, vgpu->display.port_num); in vgpu_update_vblank_emulation()
629 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) in emulate_vblank_on_pipe() argument
631 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_vblank_on_pipe()
632 struct intel_vgpu_irq *irq = &vgpu->irq; in emulate_vblank_on_pipe()
646 if (!pipe_is_enabled(vgpu, pipe)) in emulate_vblank_on_pipe()
649 intel_vgpu_trigger_virtual_event(vgpu, event); in emulate_vblank_on_pipe()
652 if (pipe_is_enabled(vgpu, pipe)) { in emulate_vblank_on_pipe()
653 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++; in emulate_vblank_on_pipe()
654 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); in emulate_vblank_on_pipe()
658 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) in intel_vgpu_emulate_vblank() argument
662 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
663 for_each_pipe(vgpu->gvt->gt->i915, pipe) in intel_vgpu_emulate_vblank()
664 emulate_vblank_on_pipe(vgpu, pipe); in intel_vgpu_emulate_vblank()
665 mutex_unlock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
669 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
670 * @vgpu: a vGPU
673 * This function is used to trigger hotplug interrupt for vGPU
676 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) in intel_vgpu_emulate_hotplug() argument
678 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_hotplug()
686 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
688 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
690 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
692 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
694 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
695 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
697 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); in intel_vgpu_emulate_hotplug()
699 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in intel_vgpu_emulate_hotplug()
701 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
704 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
707 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
709 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
711 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
713 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); in intel_vgpu_emulate_hotplug()
715 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in intel_vgpu_emulate_hotplug()
717 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
719 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
722 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
724 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
727 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
729 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
731 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
733 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); in intel_vgpu_emulate_hotplug()
735 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { in intel_vgpu_emulate_hotplug()
737 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
739 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
742 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
744 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
747 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
749 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
751 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
753 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); in intel_vgpu_emulate_hotplug()
759 * intel_vgpu_clean_display - clean vGPU virtual display emulation
760 * @vgpu: a vGPU
762 * This function is used to clean vGPU virtual display emulation stuffs
765 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) in intel_vgpu_clean_display() argument
767 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_clean_display()
773 clean_virtual_dp_monitor(vgpu, PORT_D); in intel_vgpu_clean_display()
775 clean_virtual_dp_monitor(vgpu, PORT_B); in intel_vgpu_clean_display()
777 vgpu_update_vblank_emulation(vgpu, false); in intel_vgpu_clean_display()
781 * intel_vgpu_init_display- initialize vGPU virtual display emulation
782 * @vgpu: a vGPU
785 * This function is used to initialize vGPU virtual display emulation stuffs
791 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) in intel_vgpu_init_display() argument
793 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_init_display()
795 intel_vgpu_init_i2c_edid(vgpu); in intel_vgpu_init_display()
801 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, in intel_vgpu_init_display()
804 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, in intel_vgpu_init_display()
809 * intel_vgpu_reset_display- reset vGPU virtual display emulation
810 * @vgpu: a vGPU
812 * This function is used to reset vGPU virtual display emulation stuffs
815 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) in intel_vgpu_reset_display() argument
817 emulate_monitor_status_change(vgpu); in intel_vgpu_reset_display()