Lines Matching refs:ADDR_FIX_1
388 #define ADDR_FIX_1(x1) (1 << (x1)) macro
389 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
390 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
391 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
392 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
2101 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2105 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2117 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2123 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2127 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2131 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2143 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2146 ADDR_FIX_1(2), 8, NULL},
2151 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2159 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2172 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2180 ADDR_FIX_1(3), 8, NULL},
2186 ADDR_FIX_1(4), 8, NULL},
2192 ADDR_FIX_1(4), 8, NULL},
2213 D_ALL, ADDR_FIX_1(4), 8, NULL},
2216 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2219 D_ALL, ADDR_FIX_1(4), 8, NULL},
2235 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2402 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2459 D_ALL, ADDR_FIX_1(2), 8, NULL},
2483 D_ALL, ADDR_FIX_1(2), 8, NULL},
2486 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2517 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2520 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2524 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2530 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2538 ADDR_FIX_1(1), 8, NULL},
2546 ADDR_FIX_1(1), 8, NULL},
2658 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},