Lines Matching full:vgpu
60 * @vgpu: target vgpu
69 static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, in vgpu_pci_cfg_mem_write() argument
72 u8 *cfg_base = vgpu_cfg_space(vgpu); in vgpu_pci_cfg_mem_write()
97 if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) { in vgpu_pci_cfg_mem_write()
98 pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off]) in vgpu_pci_cfg_mem_write()
101 vgpu->d3_entered = true; in vgpu_pci_cfg_mem_write()
102 gvt_dbg_core("vgpu-%d power status changed to %d\n", in vgpu_pci_cfg_mem_write()
103 vgpu->id, pwr); in vgpu_pci_cfg_mem_write()
108 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
109 * @vgpu: target vgpu
117 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, in intel_vgpu_emulate_cfg_read() argument
120 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_cfg_read()
126 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_read()
129 memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes); in intel_vgpu_emulate_cfg_read()
133 static void map_aperture(struct intel_vgpu *vgpu, bool map) in map_aperture() argument
135 if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) in map_aperture()
136 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; in map_aperture()
139 static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap) in trap_gttmmio() argument
141 if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) in trap_gttmmio()
142 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; in trap_gttmmio()
145 static int emulate_pci_command_write(struct intel_vgpu *vgpu, in emulate_pci_command_write() argument
148 u8 old = vgpu_cfg_space(vgpu)[offset]; in emulate_pci_command_write()
152 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); in emulate_pci_command_write()
157 trap_gttmmio(vgpu, false); in emulate_pci_command_write()
158 map_aperture(vgpu, false); in emulate_pci_command_write()
160 trap_gttmmio(vgpu, true); in emulate_pci_command_write()
161 map_aperture(vgpu, true); in emulate_pci_command_write()
167 static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, in emulate_pci_rom_bar_write() argument
170 u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); in emulate_pci_rom_bar_write()
177 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); in emulate_pci_rom_bar_write()
181 static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, in emulate_pci_bar_write() argument
188 vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; in emulate_pci_bar_write()
189 struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; in emulate_pci_bar_write()
203 intel_vgpu_write_pci_bar(vgpu, offset, in emulate_pci_bar_write()
209 trap_gttmmio(vgpu, false); in emulate_pci_bar_write()
214 intel_vgpu_write_pci_bar(vgpu, offset, in emulate_pci_bar_write()
216 map_aperture(vgpu, false); in emulate_pci_bar_write()
220 intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false); in emulate_pci_bar_write()
230 trap_gttmmio(vgpu, false); in emulate_pci_bar_write()
231 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); in emulate_pci_bar_write()
232 trap_gttmmio(vgpu, mmio_enabled); in emulate_pci_bar_write()
236 map_aperture(vgpu, false); in emulate_pci_bar_write()
237 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); in emulate_pci_bar_write()
238 map_aperture(vgpu, mmio_enabled); in emulate_pci_bar_write()
241 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); in emulate_pci_bar_write()
247 * intel_vgpu_emulate_cfg_write - emulate vGPU configuration space write
248 * @vgpu: target vgpu
256 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, in intel_vgpu_emulate_cfg_write() argument
259 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_cfg_write()
266 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_write()
273 return emulate_pci_command_write(vgpu, offset, p_data, bytes); in intel_vgpu_emulate_cfg_write()
280 return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes); in intel_vgpu_emulate_cfg_write()
285 emulate_pci_bar_write(vgpu, offset, p_data, bytes); in intel_vgpu_emulate_cfg_write()
290 ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data); in intel_vgpu_emulate_cfg_write()
298 ret = intel_vgpu_opregion_base_write_handler(vgpu, in intel_vgpu_emulate_cfg_write()
303 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); in intel_vgpu_emulate_cfg_write()
306 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); in intel_vgpu_emulate_cfg_write()
313 * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU
315 * @vgpu: a vGPU
316 * @primary: is the vGPU presented as primary
319 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, in intel_vgpu_init_cfg_space() argument
322 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_init_cfg_space()
328 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, in intel_vgpu_init_cfg_space()
332 vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] = in intel_vgpu_init_cfg_space() local
334 vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] = in intel_vgpu_init_cfg_space() local
339 gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL); in intel_vgpu_init_cfg_space()
342 intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2, in intel_vgpu_init_cfg_space()
345 vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO in intel_vgpu_init_cfg_space() local
351 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); in intel_vgpu_init_cfg_space()
352 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); in intel_vgpu_init_cfg_space()
353 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8); in intel_vgpu_init_cfg_space()
354 memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); in intel_vgpu_init_cfg_space()
356 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = in intel_vgpu_init_cfg_space()
358 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = in intel_vgpu_init_cfg_space()
361 memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4); in intel_vgpu_init_cfg_space()
364 vgpu->cfg_space.pmcsr_off = 0; in intel_vgpu_init_cfg_space()
365 if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) { in intel_vgpu_init_cfg_space()
366 next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST]; in intel_vgpu_init_cfg_space()
368 if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) { in intel_vgpu_init_cfg_space() local
369 vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL; in intel_vgpu_init_cfg_space()
372 next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT]; in intel_vgpu_init_cfg_space()
378 * intel_vgpu_reset_cfg_space - reset vGPU configuration space
380 * @vgpu: a vGPU
383 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu) in intel_vgpu_reset_cfg_space() argument
385 u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND]; in intel_vgpu_reset_cfg_space()
386 bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] != in intel_vgpu_reset_cfg_space()
390 trap_gttmmio(vgpu, false); in intel_vgpu_reset_cfg_space()
391 map_aperture(vgpu, false); in intel_vgpu_reset_cfg_space()
395 * Currently we only do such reset when vGPU is not in intel_vgpu_reset_cfg_space()
399 intel_vgpu_init_cfg_space(vgpu, primary); in intel_vgpu_reset_cfg_space()