2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
24  *    Eddie Dong <eddie.dong@intel.com>
25  *    Jike Song <jike.song@intel.com>
28  *    Zhi Wang <zhi.a.wang@intel.com>
29  *    Min He <min.he@intel.com>
30  *    Bing Niu <bing.niu@intel.com>
45 /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one
53 	[PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
59  * vgpu_pci_cfg_mem_write - write virtual cfg space memory
61  * @off: offset
95 		memcpy(cfg_base + off + i, src + i, bytes - i);  in vgpu_pci_cfg_mem_write()
97 	if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) {  in vgpu_pci_cfg_mem_write()
101 			vgpu->d3_entered = true;  in vgpu_pci_cfg_mem_write()
102 		gvt_dbg_core("vgpu-%d power status changed to %d\n",  in vgpu_pci_cfg_mem_write()
103 			     vgpu->id, pwr);  in vgpu_pci_cfg_mem_write()
108  * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
110  * @offset: offset
117 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,  in intel_vgpu_emulate_cfg_read()  argument
120 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_vgpu_emulate_cfg_read()
122 	if (drm_WARN_ON(&i915->drm, bytes > 4))  in intel_vgpu_emulate_cfg_read()
123 		return -EINVAL;  in intel_vgpu_emulate_cfg_read()
125 	if (drm_WARN_ON(&i915->drm,  in intel_vgpu_emulate_cfg_read()
126 			offset + bytes > vgpu->gvt->device_info.cfg_space_size))  in intel_vgpu_emulate_cfg_read()
127 		return -EINVAL;  in intel_vgpu_emulate_cfg_read()
129 	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);  in intel_vgpu_emulate_cfg_read()
135 	if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)  in map_aperture()
136 		vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;  in map_aperture()
141 	if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)  in trap_gttmmio()
142 		vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;  in trap_gttmmio()
146 	unsigned int offset, void *p_data, unsigned int bytes)  in emulate_pci_command_write()  argument
148 	u8 old = vgpu_cfg_space(vgpu)[offset];  in emulate_pci_command_write()
152 	vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);  in emulate_pci_command_write()
168 	unsigned int offset, void *p_data, unsigned int bytes)  in emulate_pci_rom_bar_write()  argument
170 	u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);  in emulate_pci_rom_bar_write()
177 		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);  in emulate_pci_rom_bar_write()
181 static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,  in emulate_pci_bar_write()  argument
185 	bool lo = IS_ALIGNED(offset, 8);  in emulate_pci_bar_write()
189 	struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;  in emulate_pci_bar_write()
192 	 * Power-up software can determine how much address  in emulate_pci_bar_write()
195 	 * back. The device will return 0's in all don't-care  in emulate_pci_bar_write()
199 		switch (offset) {  in emulate_pci_bar_write()
202 			size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1);  in emulate_pci_bar_write()
203 			intel_vgpu_write_pci_bar(vgpu, offset,  in emulate_pci_bar_write()
213 			size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);  in emulate_pci_bar_write()
214 			intel_vgpu_write_pci_bar(vgpu, offset,  in emulate_pci_bar_write()
220 			intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);  in emulate_pci_bar_write()
223 		switch (offset) {  in emulate_pci_bar_write()
228 			 * re-configured the BAR  in emulate_pci_bar_write()
231 			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);  in emulate_pci_bar_write()
237 			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);  in emulate_pci_bar_write()
241 			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);  in emulate_pci_bar_write()
247  * intel_vgpu_emulate_cfg_write - emulate vGPU configuration space write
249  * @offset: offset
256 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,  in intel_vgpu_emulate_cfg_write()  argument
259 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_vgpu_emulate_cfg_write()
262 	if (drm_WARN_ON(&i915->drm, bytes > 4))  in intel_vgpu_emulate_cfg_write()
263 		return -EINVAL;  in intel_vgpu_emulate_cfg_write()
265 	if (drm_WARN_ON(&i915->drm,  in intel_vgpu_emulate_cfg_write()
266 			offset + bytes > vgpu->gvt->device_info.cfg_space_size))  in intel_vgpu_emulate_cfg_write()
267 		return -EINVAL;  in intel_vgpu_emulate_cfg_write()
270 	if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {  in intel_vgpu_emulate_cfg_write()
271 		if (drm_WARN_ON(&i915->drm, bytes > 2))  in intel_vgpu_emulate_cfg_write()
272 			return -EINVAL;  in intel_vgpu_emulate_cfg_write()
273 		return emulate_pci_command_write(vgpu, offset, p_data, bytes);  in intel_vgpu_emulate_cfg_write()
276 	switch (rounddown(offset, 4)) {  in intel_vgpu_emulate_cfg_write()
278 		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))  in intel_vgpu_emulate_cfg_write()
279 			return -EINVAL;  in intel_vgpu_emulate_cfg_write()
280 		return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);  in intel_vgpu_emulate_cfg_write()
283 		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))  in intel_vgpu_emulate_cfg_write()
284 			return -EINVAL;  in intel_vgpu_emulate_cfg_write()
285 		emulate_pci_bar_write(vgpu, offset, p_data, bytes);  in intel_vgpu_emulate_cfg_write()
288 		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))  in intel_vgpu_emulate_cfg_write()
289 			return -EINVAL;  in intel_vgpu_emulate_cfg_write()
296 		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))  in intel_vgpu_emulate_cfg_write()
297 			return -EINVAL;  in intel_vgpu_emulate_cfg_write()
303 		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);  in intel_vgpu_emulate_cfg_write()
306 		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);  in intel_vgpu_emulate_cfg_write()
313  * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU
322 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_init_cfg_space()
323 	struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);  in intel_vgpu_init_cfg_space()
324 	const struct intel_gvt_device_info *info = &gvt->device_info;  in intel_vgpu_init_cfg_space()
328 	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,  in intel_vgpu_init_cfg_space()
329 	       info->cfg_space_size);  in intel_vgpu_init_cfg_space()
356 	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =  in intel_vgpu_init_cfg_space()
358 	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =  in intel_vgpu_init_cfg_space()
364 	vgpu->cfg_space.pmcsr_off = 0;  in intel_vgpu_init_cfg_space()
369 				vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL;  in intel_vgpu_init_cfg_space()
378  * intel_vgpu_reset_cfg_space - reset vGPU configuration space