Lines Matching +full:max +full:- +full:rpm
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
44 struct intel_gvt *gvt = vgpu->gvt; in alloc_gm()
45 struct intel_gt *gt = gvt->gt; in alloc_gm()
52 node = &vgpu->gm.high_gm_node; in alloc_gm()
58 node = &vgpu->gm.low_gm_node; in alloc_gm()
65 mutex_lock(>->ggtt->vm.mutex); in alloc_gm()
67 ret = i915_gem_gtt_insert(>->ggtt->vm, NULL, node, in alloc_gm()
72 mutex_unlock(>->ggtt->vm.mutex); in alloc_gm()
82 struct intel_gvt *gvt = vgpu->gvt; in alloc_vgpu_gm()
83 struct intel_gt *gt = gvt->gt; in alloc_vgpu_gm()
94 gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id, in alloc_vgpu_gm()
97 gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id, in alloc_vgpu_gm()
102 mutex_lock(>->ggtt->vm.mutex); in alloc_vgpu_gm()
103 drm_mm_remove_node(&vgpu->gm.low_gm_node); in alloc_vgpu_gm()
104 mutex_unlock(>->ggtt->vm.mutex); in alloc_vgpu_gm()
110 struct intel_gvt *gvt = vgpu->gvt; in free_vgpu_gm()
111 struct intel_gt *gt = gvt->gt; in free_vgpu_gm()
113 mutex_lock(>->ggtt->vm.mutex); in free_vgpu_gm()
114 drm_mm_remove_node(&vgpu->gm.low_gm_node); in free_vgpu_gm()
115 drm_mm_remove_node(&vgpu->gm.high_gm_node); in free_vgpu_gm()
116 mutex_unlock(>->ggtt->vm.mutex); in free_vgpu_gm()
120 * intel_vgpu_write_fence - write fence registers owned by a vGPU
132 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_write_fence()
133 struct drm_i915_private *i915 = gvt->gt->i915; in intel_vgpu_write_fence()
134 struct intel_uncore *uncore = gvt->gt->uncore; in intel_vgpu_write_fence()
138 assert_rpm_wakelock_held(uncore->rpm); in intel_vgpu_write_fence()
140 if (drm_WARN_ON(&i915->drm, fence >= vgpu_fence_sz(vgpu))) in intel_vgpu_write_fence()
143 reg = vgpu->fence.regs[fence]; in intel_vgpu_write_fence()
144 if (drm_WARN_ON(&i915->drm, !reg)) in intel_vgpu_write_fence()
147 fence_reg_lo = FENCE_REG_GEN6_LO(reg->id); in intel_vgpu_write_fence()
148 fence_reg_hi = FENCE_REG_GEN6_HI(reg->id); in intel_vgpu_write_fence()
168 struct intel_gvt *gvt = vgpu->gvt; in free_vgpu_fence()
169 struct intel_uncore *uncore = gvt->gt->uncore; in free_vgpu_fence()
174 if (drm_WARN_ON(&gvt->gt->i915->drm, !vgpu_fence_sz(vgpu))) in free_vgpu_fence()
177 wakeref = intel_runtime_pm_get(uncore->rpm); in free_vgpu_fence()
179 mutex_lock(&gvt->gt->ggtt->vm.mutex); in free_vgpu_fence()
182 reg = vgpu->fence.regs[i]; in free_vgpu_fence()
184 vgpu->fence.regs[i] = NULL; in free_vgpu_fence()
186 mutex_unlock(&gvt->gt->ggtt->vm.mutex); in free_vgpu_fence()
188 intel_runtime_pm_put(uncore->rpm, wakeref); in free_vgpu_fence()
193 struct intel_gvt *gvt = vgpu->gvt; in alloc_vgpu_fence()
194 struct intel_uncore *uncore = gvt->gt->uncore; in alloc_vgpu_fence()
199 wakeref = intel_runtime_pm_get(uncore->rpm); in alloc_vgpu_fence()
202 mutex_lock(&gvt->gt->ggtt->vm.mutex); in alloc_vgpu_fence()
205 reg = i915_reserve_fence(gvt->gt->ggtt); in alloc_vgpu_fence()
209 vgpu->fence.regs[i] = reg; in alloc_vgpu_fence()
214 mutex_unlock(&gvt->gt->ggtt->vm.mutex); in alloc_vgpu_fence()
215 intel_runtime_pm_put(uncore->rpm, wakeref); in alloc_vgpu_fence()
222 reg = vgpu->fence.regs[i]; in alloc_vgpu_fence()
226 vgpu->fence.regs[i] = NULL; in alloc_vgpu_fence()
228 mutex_unlock(&gvt->gt->ggtt->vm.mutex); in alloc_vgpu_fence()
229 intel_runtime_pm_put_unchecked(uncore->rpm); in alloc_vgpu_fence()
230 return -ENOSPC; in alloc_vgpu_fence()
235 struct intel_gvt *gvt = vgpu->gvt; in free_resource()
237 gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu); in free_resource()
238 gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu); in free_resource()
239 gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu); in free_resource()
245 struct intel_gvt *gvt = vgpu->gvt; in alloc_resource()
246 unsigned long request, avail, max, taken; in alloc_resource() local
249 if (!conf->low_mm || !conf->high_mm || !conf->fence) { in alloc_resource()
251 return -EINVAL; in alloc_resource()
255 max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; in alloc_resource()
256 taken = gvt->gm.vgpu_allocated_low_gm_size; in alloc_resource()
257 avail = max - taken; in alloc_resource()
258 request = conf->low_mm; in alloc_resource()
266 max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; in alloc_resource()
267 taken = gvt->gm.vgpu_allocated_high_gm_size; in alloc_resource()
268 avail = max - taken; in alloc_resource()
269 request = conf->high_mm; in alloc_resource()
277 max = gvt_fence_sz(gvt) - HOST_FENCE; in alloc_resource()
278 taken = gvt->fence.vgpu_allocated_fence_num; in alloc_resource()
279 avail = max - taken; in alloc_resource()
280 request = conf->fence; in alloc_resource()
287 gvt->gm.vgpu_allocated_low_gm_size += conf->low_mm; in alloc_resource()
288 gvt->gm.vgpu_allocated_high_gm_size += conf->high_mm; in alloc_resource()
289 gvt->fence.vgpu_allocated_fence_num += conf->fence; in alloc_resource()
294 gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n", in alloc_resource()
296 BYTES_TO_MB(max), BYTES_TO_MB(taken)); in alloc_resource()
297 return -ENOSPC; in alloc_resource()
301 * intel_vgpu_free_resource() - free HW resource owned by a vGPU
315 * intel_vgpu_reset_resource - reset resource state owned by a vGPU
323 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reset_resource()
326 with_intel_runtime_pm(gvt->gt->uncore->rpm, wakeref) in intel_vgpu_reset_resource()
331 * intel_vgpu_alloc_resource() - allocate HW resource for a vGPU