gt/uc/intel_guc.h

1 /* SPDX-License-Identifier: MIT */
3  * Copyright © 2014-2019 Intel Corporation
10 #include <linux/iosys-map.h>
28  * struct intel_guc - Top level structure of GuC.
30  * It handles firmware loading and manages client pool. intel_guc owns an
34 	/** @fw: the GuC firmware */
36 	/** @log: sub-structure containing GuC log related data and objects */
40 	/** @slpc: sub-structure containing SLPC related data and objects */
42 	/** @capture: the error-state-capture module's data and objects */
94 	/** @interrupts: pointers to GuC interrupt-managing functions. */
103 	 * @submission_state: sub-structure for submission state protected by
109 		 * submission_state, ce->guc_id.id, and ce->guc_id.ref
115 		 * guc_ids, single-lrc
125 		 * new guc_ids, multi-lrc
134 		 * @submission_state.guc_ids_in_use: Number single-lrc
180 	/** @submission_initialized: tracks whether GuC submission has been initialised */
182 	/** @submission_version: Submission API version of the currently loaded firmware */
258 		 * @timestamp.gt_stamp: 64-bit extended value of the GT
322  * GuC version number components are only 8-bit, so converting to a 32bit 8.8.8
327 #define GUC_SUBMIT_VER(guc)		MAKE_GUC_VER_STRUCT((guc)->submission_version)
328 #define GUC_FIRMWARE_VER(guc)		MAKE_GUC_VER_STRUCT((guc)->fw.file_selected.ver)
338 	return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 0);  in intel_guc_send()
345 	return intel_guc_ct_send(&guc->ct, action, len, NULL, 0,  in intel_guc_send_nb()
353 	return intel_guc_ct_send(&guc->ct, action, len,  in intel_guc_send_and_receive()
379 	if (unlikely(err == -EBUSY && loop)) {  in intel_guc_send_busy_loop()
382 				return -EINTR;  in intel_guc_send_busy_loop()
396 	if (guc->interrupts.enabled)  in intel_guc_to_host_event_handler()
397 		intel_guc_ct_event_handler(&guc->ct);  in intel_guc_to_host_event_handler()
404  * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
422 	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));  in intel_guc_ggtt_offset()
449 	return intel_uc_fw_is_supported(&guc->fw);  in intel_guc_is_supported()
454 	return intel_uc_fw_is_enabled(&guc->fw);  in intel_guc_is_wanted()
459 	GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED);  in intel_guc_is_used()
460 	return intel_uc_fw_is_available(&guc->fw);  in intel_guc_is_used()
465 	return intel_uc_fw_is_running(&guc->fw);  in intel_guc_is_fw_running()
470 	return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(&guc->ct);  in intel_guc_is_ready()
475 	guc->interrupts.reset(guc);  in intel_guc_reset_interrupts()
480 	guc->interrupts.enable(guc);  in intel_guc_enable_interrupts()
485 	guc->interrupts.disable(guc);  in intel_guc_disable_interrupts()
490 	intel_uc_fw_sanitize(&guc->fw);  in intel_guc_sanitize()
492 	intel_guc_ct_sanitize(&guc->ct);  in intel_guc_sanitize()
493 	guc->mmio_msg = 0;  in intel_guc_sanitize()
500 	spin_lock_irq(&guc->irq_lock);  in intel_guc_enable_msg()
501 	guc->msg_enabled_mask |= mask;  in intel_guc_enable_msg()
502 	spin_unlock_irq(&guc->irq_lock);  in intel_guc_enable_msg()
507 	spin_lock_irq(&guc->irq_lock);  in intel_guc_disable_msg()
508 	guc->msg_enabled_mask &= ~mask;  in intel_guc_disable_msg()
509 	spin_unlock_irq(&guc->irq_lock);  in intel_guc_disable_msg()