Lines Matching full:engine
34 } engine[I915_NUM_ENGINES]; member
64 struct intel_engine_cs *engine; in reference_lists_init() local
73 for_each_engine(engine, gt, id) { in reference_lists_init()
74 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
76 wa_init_start(wal, gt, "REF", engine->name); in reference_lists_init()
77 engine_init_workarounds(engine, wal); in reference_lists_init()
80 __intel_engine_init_ctx_wa(engine, in reference_lists_init()
81 &lists->engine[id].ctx_wa_list, in reference_lists_init()
89 struct intel_engine_cs *engine; in reference_lists_fini() local
92 for_each_engine(engine, gt, id) in reference_lists_fini()
93 intel_wa_list_free(&lists->engine[id].wa_list); in reference_lists_fini()
101 struct intel_engine_cs *engine = ce->engine; in read_nonprivs() local
102 const u32 base = engine->mmio_base; in read_nonprivs()
110 result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); in read_nonprivs()
125 vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL); in read_nonprivs()
146 if (GRAPHICS_VER(engine->i915) >= 8) in read_nonprivs()
178 get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i) in get_whitelist_reg() argument
180 i915_reg_t reg = i < engine->whitelist.count ? in get_whitelist_reg()
181 engine->whitelist.list[i].reg : in get_whitelist_reg()
182 RING_NOPID(engine->mmio_base); in get_whitelist_reg()
188 print_results(const struct intel_engine_cs *engine, const u32 *results) in print_results() argument
193 u32 expected = get_whitelist_reg(engine, i); in print_results()
203 struct intel_engine_cs *engine = ce->engine; in check_whitelist() local
216 intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */ in check_whitelist()
219 if (intel_gt_is_wedged(engine->gt)) in check_whitelist()
231 u32 expected = get_whitelist_reg(engine, i); in check_whitelist()
235 print_results(engine, vaddr); in check_whitelist()
251 static int do_device_reset(struct intel_engine_cs *engine) in do_device_reset() argument
253 intel_gt_reset(engine->gt, engine->mask, "live_workarounds"); in do_device_reset()
257 static int do_engine_reset(struct intel_engine_cs *engine) in do_engine_reset() argument
259 return intel_engine_reset(engine, "live_workarounds"); in do_engine_reset()
262 static int do_guc_reset(struct intel_engine_cs *engine) in do_guc_reset() argument
269 switch_to_scratch_context(struct intel_engine_cs *engine, in switch_to_scratch_context() argument
276 ce = intel_context_create(engine); in switch_to_scratch_context()
297 static int check_whitelist_across_reset(struct intel_engine_cs *engine, in check_whitelist_across_reset() argument
308 engine->whitelist.count, engine->name, name); in check_whitelist_across_reset()
310 ce = intel_context_create(engine); in check_whitelist_across_reset()
314 err = igt_spinner_init(&spin, engine->gt); in check_whitelist_across_reset()
324 err = switch_to_scratch_context(engine, &spin, &rq); in check_whitelist_across_reset()
335 with_intel_runtime_pm(engine->uncore->rpm, wakeref) in check_whitelist_across_reset()
336 err = reset(engine); in check_whitelist_across_reset()
338 /* Ensure the reset happens and kills the engine */ in check_whitelist_across_reset()
356 tmp = intel_context_create(engine); in check_whitelist_across_reset()
418 static bool wo_register(struct intel_engine_cs *engine, u32 reg) in wo_register() argument
420 enum intel_platform platform = INTEL_INFO(engine->i915)->platform; in wo_register()
436 static bool timestamp(const struct intel_engine_cs *engine, u32 reg) in timestamp() argument
438 reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK; in timestamp()
459 static int whitelist_writable_count(struct intel_engine_cs *engine) in whitelist_writable_count() argument
461 int count = engine->whitelist.count; in whitelist_writable_count()
464 for (i = 0; i < engine->whitelist.count; i++) { in whitelist_writable_count()
465 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
502 struct intel_engine_cs *engine = ce->engine; in check_dirty_whitelist() local
519 for (i = 0; i < engine->whitelist.count; i++) { in check_dirty_whitelist()
520 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
529 if (wo_register(engine, reg)) in check_dirty_whitelist()
532 if (timestamp(engine, reg)) in check_dirty_whitelist()
565 if (GRAPHICS_VER(engine->i915) >= 8) in check_dirty_whitelist()
569 engine->name, reg); in check_dirty_whitelist()
616 intel_gt_chipset_flush(engine->gt); in check_dirty_whitelist()
625 if (engine->emit_init_breadcrumb) { /* Be nice if we hang */ in check_dirty_whitelist()
626 err = engine->emit_init_breadcrumb(rq); in check_dirty_whitelist()
640 err = engine->emit_bb_start(rq, in check_dirty_whitelist()
650 engine->name, reg); in check_dirty_whitelist()
651 intel_gt_set_wedged(engine->gt); in check_dirty_whitelist()
661 engine->name, reg); in check_dirty_whitelist()
693 engine->name, err, reg); in check_dirty_whitelist()
697 engine->name, reg, results[0]); in check_dirty_whitelist()
700 engine->name, reg, results[0], rsvd); in check_dirty_whitelist()
747 if (igt_flush_test(engine->i915)) in check_dirty_whitelist()
759 struct intel_engine_cs *engine; in live_dirty_whitelist() local
767 for_each_engine(engine, gt, id) { in live_dirty_whitelist()
771 if (engine->whitelist.count == 0) in live_dirty_whitelist()
774 ce = intel_context_create(engine); in live_dirty_whitelist()
790 struct intel_engine_cs *engine; in live_reset_whitelist() local
797 for_each_engine(engine, gt, id) { in live_reset_whitelist()
798 if (engine->whitelist.count == 0) in live_reset_whitelist()
802 if (intel_engine_uses_guc(engine)) { in live_reset_whitelist()
806 err = intel_selftest_modify_policy(engine, &saved, in live_reset_whitelist()
811 err = check_whitelist_across_reset(engine, in live_reset_whitelist()
815 err2 = intel_selftest_restore_policy(engine, &saved); in live_reset_whitelist()
819 err = check_whitelist_across_reset(engine, in live_reset_whitelist()
821 "engine"); in live_reset_whitelist()
829 err = check_whitelist_across_reset(engine, in live_reset_whitelist()
845 struct intel_engine_cs *engine = ce->engine; in read_whitelisted_registers() local
859 if (GRAPHICS_VER(engine->i915) >= 8) in read_whitelisted_registers()
862 cs = intel_ring_begin(rq, 4 * engine->whitelist.count); in read_whitelisted_registers()
868 for (i = 0; i < engine->whitelist.count; i++) { in read_whitelisted_registers()
870 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
888 struct intel_engine_cs *engine = ce->engine; in scrub_whitelisted_registers() local
904 *cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine)); in scrub_whitelisted_registers()
905 for (i = 0; i < engine->whitelist.count; i++) { in scrub_whitelisted_registers()
906 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
920 intel_gt_chipset_flush(engine->gt); in scrub_whitelisted_registers()
928 if (engine->emit_init_breadcrumb) { /* Be nice if we hang */ in scrub_whitelisted_registers()
929 err = engine->emit_init_breadcrumb(rq); in scrub_whitelisted_registers()
939 err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0); in scrub_whitelisted_registers()
984 static bool result_eq(struct intel_engine_cs *engine, in result_eq() argument
987 if (a != b && !pardon_reg(engine->i915, reg)) { in result_eq()
1006 static bool result_neq(struct intel_engine_cs *engine, in result_neq() argument
1009 if (a == b && !writeonly_reg(engine->i915, reg)) { in result_neq()
1019 check_whitelisted_registers(struct intel_engine_cs *engine, in check_whitelisted_registers() argument
1022 bool (*fn)(struct intel_engine_cs *engine, in check_whitelisted_registers() argument
1040 for (i = 0; i < engine->whitelist.count; i++) { in check_whitelisted_registers()
1041 const struct i915_wa *wa = &engine->whitelist.list[i]; in check_whitelisted_registers()
1047 if (!fn(engine, a[i], b[i], wa->reg)) in check_whitelisted_registers()
1063 struct intel_engine_cs *engine; in live_isolated_whitelist() local
1092 for_each_engine(engine, gt, id) { in live_isolated_whitelist()
1095 if (!engine->kernel_context->vm) in live_isolated_whitelist()
1098 if (!whitelist_writable_count(engine)) in live_isolated_whitelist()
1101 ce[0] = intel_context_create(engine); in live_isolated_whitelist()
1106 ce[1] = intel_context_create(engine); in live_isolated_whitelist()
1129 err = check_whitelisted_registers(engine, in live_isolated_whitelist()
1142 err = check_whitelisted_registers(engine, in live_isolated_whitelist()
1169 struct intel_engine_cs *engine; in verify_wa_lists() local
1175 for_each_engine(engine, gt, id) { in verify_wa_lists()
1178 ce = intel_context_create(engine); in verify_wa_lists()
1183 &lists->engine[id].wa_list, in verify_wa_lists()
1187 &lists->engine[id].ctx_wa_list, in verify_wa_lists()
1239 struct intel_engine_cs *engine; in live_engine_reset_workarounds() local
1260 for_each_engine(engine, gt, id) { in live_engine_reset_workarounds()
1262 bool using_guc = intel_engine_uses_guc(engine); in live_engine_reset_workarounds()
1266 pr_info("Verifying after %s reset...\n", engine->name); in live_engine_reset_workarounds()
1267 ret = intel_selftest_modify_policy(engine, &saved, in live_engine_reset_workarounds()
1272 ce = intel_context_create(engine); in live_engine_reset_workarounds()
1285 ret = intel_engine_reset(engine, "live_workarounds:idle"); in live_engine_reset_workarounds()
1287 pr_err("%s: Reset failed while idle\n", engine->name); in live_engine_reset_workarounds()
1298 ret = igt_spinner_init(&spin, engine->gt); in live_engine_reset_workarounds()
1311 pr_err("%s: Spinner failed to start\n", engine->name); in live_engine_reset_workarounds()
1323 ret = intel_engine_reset(engine, "live_workarounds:active"); in live_engine_reset_workarounds()
1326 engine->name); in live_engine_reset_workarounds()
1332 /* Ensure the reset happens and kills the engine */ in live_engine_reset_workarounds()
1348 ret2 = intel_selftest_restore_policy(engine, &saved); in live_engine_reset_workarounds()