Lines Matching +full:re +full:- +full:tuning
1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014-2018 Intel Corporation
30 * - Context workarounds: workarounds that touch registers that are
40 * - Engine workarounds: the list of these WAs is applied whenever the specific
60 * - GT workarounds: the list of these WAs is applied whenever these registers
66 * - Register whitelist: some workarounds need to be implemented in userspace,
70 * these to/be-whitelisted registers to some special HW registers).
75 * - Workaround batchbuffers: buffers that get executed automatically by the
91 * - Other: There are WAs that, due to their nature, cannot be applied from a
103 wal->gt = gt; in wa_init_start()
104 wal->name = name; in wa_init_start()
105 wal->engine_name = engine_name; in wa_init_start()
113 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { in wa_init_finish()
114 struct i915_wa *list = kmemdup_array(wal->list, wal->count, in wa_init_finish()
118 kfree(wal->list); in wa_init_finish()
119 wal->list = list; in wa_init_finish()
123 if (!wal->count) in wa_init_finish()
126 gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n", in wa_init_finish()
127 wal->wa_count, wal->name, wal->engine_name); in wa_init_finish()
137 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wal_get_fw_for_rmw()
139 wa->reg, in wal_get_fw_for_rmw()
148 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
149 struct drm_i915_private *i915 = wal->gt->i915; in _wa_add()
150 unsigned int start = 0, end = wal->count; in _wa_add()
156 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ in _wa_add()
159 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), in _wa_add()
162 drm_err(&i915->drm, "No space for workaround init!\n"); in _wa_add()
166 if (wal->list) { in _wa_add()
167 memcpy(list, wal->list, sizeof(*wa) * wal->count); in _wa_add()
168 kfree(wal->list); in _wa_add()
171 wal->list = list; in _wa_add()
175 unsigned int mid = start + (end - start) / 2; in _wa_add()
177 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
179 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
182 wa_ = &wal->list[mid]; in _wa_add()
184 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { in _wa_add()
185 drm_err(&i915->drm, in _wa_add()
187 i915_mmio_reg_offset(wa_->reg), in _wa_add()
188 wa_->clr, wa_->set); in _wa_add()
190 wa_->set &= ~wa->clr; in _wa_add()
193 wal->wa_count++; in _wa_add()
194 wa_->set |= wa->set; in _wa_add()
195 wa_->clr |= wa->clr; in _wa_add()
196 wa_->read |= wa->read; in _wa_add()
201 wal->wa_count++; in _wa_add()
202 wa_ = &wal->list[wal->count++]; in _wa_add()
205 while (wa_-- > wal->list) { in _wa_add()
289 * documented as "masked" in b-spec. Its purpose is to allow writing to just a
360 /* Use Force Non-Coherent whenever executing a 3D context. This is a in gen8_ctx_workarounds_init()
371 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping in gen8_ctx_workarounds_init()
399 struct drm_i915_private *i915 = engine->i915; in bdw_ctx_workarounds_init()
403 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ in bdw_ctx_workarounds_init()
420 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ in bdw_ctx_workarounds_init()
439 struct drm_i915_private *i915 = engine->i915; in gen9_ctx_workarounds_init()
488 * Use Force Non-Coherent whenever executing a 3D context. This in gen9_ctx_workarounds_init()
509 * Supporting preemption with fine-granularity requires changes in the in gen9_ctx_workarounds_init()
512 * still able to use more fine-grained preemption levels, since in in gen9_ctx_workarounds_init()
513 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the in gen9_ctx_workarounds_init()
514 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are in gen9_ctx_workarounds_init()
535 struct intel_gt *gt = engine->gt; in skl_tune_iz_hashing()
546 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
553 * -> 0 <= ss <= 3; in skl_tune_iz_hashing()
555 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
556 vals[i] = 3 - ss; in skl_tune_iz_hashing()
596 struct drm_i915_private *i915 = engine->i915; in kbl_ctx_workarounds_init()
652 0 /* write-only, so skip validation */, in icl_ctx_workarounds_init()
675 * These settings aren't actually workarounds, but general tuning settings that
691 struct drm_i915_private *i915 = engine->i915; in gen12_ctx_workarounds_init()
694 * Wa_1409142259:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
695 * Wa_1409347922:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
696 * Wa_1409252684:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
697 * Wa_1409217633:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
698 * Wa_1409207793:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
699 * Wa_1409178076:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
700 * Wa_1408979724:tgl,dg1,adl-p in gen12_ctx_workarounds_init()
701 * Wa_14010443199:tgl,rkl,dg1,adl-p in gen12_ctx_workarounds_init()
702 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p in gen12_ctx_workarounds_init()
703 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p in gen12_ctx_workarounds_init()
714 * Wa_16011163337 - GS_TIMER in gen12_ctx_workarounds_init()
785 struct intel_gt *gt = engine->gt; in xelpg_ctx_gt_tuning_init()
790 * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in in xelpg_ctx_gt_tuning_init()
802 struct intel_gt *gt = engine->gt; in xelpg_ctx_workarounds_init()
835 * maintain reliable, backward-compatible behavior for userspace with in fakewa_disable_nestedbb_mode()
838 * The per-context setting of MI_MODE[12] determines whether the bits in fakewa_disable_nestedbb_mode()
842 * into 3rd-level batchbuffers. When this new capability was first in fakewa_disable_nestedbb_mode()
848 * From a SW perspective, we want to maintain the backward-compatible in fakewa_disable_nestedbb_mode()
852 * userspace that utilizes third-level batchbuffers, so this will avoid in fakewa_disable_nestedbb_mode()
855 * consumers that want to utilize third-level batch nesting, we can in fakewa_disable_nestedbb_mode()
856 * provide a context parameter to allow them to opt-in. in fakewa_disable_nestedbb_mode()
858 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); in fakewa_disable_nestedbb_mode()
869 * BLIT_CCTL registers are needed to be programmed to un-cached. in gen12_ctx_gt_mocs_init()
871 if (engine->class == COPY_ENGINE_CLASS) { in gen12_ctx_gt_mocs_init()
872 mocs = engine->gt->mocs.uc_index; in gen12_ctx_gt_mocs_init()
874 BLIT_CCTL(engine->mmio_base), in gen12_ctx_gt_mocs_init()
890 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in gen12_ctx_gt_fake_wa_init()
901 struct drm_i915_private *i915 = engine->i915; in __intel_engine_init_ctx_wa()
903 wa_init_start(wal, engine->gt, name, engine->name); in __intel_engine_init_ctx_wa()
913 if (engine->class != RENDER_CLASS) in __intel_engine_init_ctx_wa()
916 if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) in __intel_engine_init_ctx_wa()
955 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); in intel_engine_init_ctx_wa()
960 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; in intel_engine_emit_ctx_wa()
961 struct intel_uncore *uncore = rq->engine->uncore; in intel_engine_emit_ctx_wa()
969 if (wal->count == 0) in intel_engine_emit_ctx_wa()
972 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); in intel_engine_emit_ctx_wa()
976 if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) || in intel_engine_emit_ctx_wa()
977 IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS) in intel_engine_emit_ctx_wa()
978 cs = intel_ring_begin(rq, (wal->count * 2 + 6)); in intel_engine_emit_ctx_wa()
980 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); in intel_engine_emit_ctx_wa()
987 intel_gt_mcr_lock(wal->gt, &flags); in intel_engine_emit_ctx_wa()
988 spin_lock(&uncore->lock); in intel_engine_emit_ctx_wa()
991 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); in intel_engine_emit_ctx_wa()
992 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in intel_engine_emit_ctx_wa()
996 if (wa->masked_reg || (wa->clr | wa->set) == U32_MAX) { in intel_engine_emit_ctx_wa()
997 val = wa->set; in intel_engine_emit_ctx_wa()
999 val = wa->is_mcr ? in intel_engine_emit_ctx_wa()
1000 intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) : in intel_engine_emit_ctx_wa()
1001 intel_uncore_read_fw(uncore, wa->reg); in intel_engine_emit_ctx_wa()
1002 val &= ~wa->clr; in intel_engine_emit_ctx_wa()
1003 val |= wa->set; in intel_engine_emit_ctx_wa()
1006 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
1012 if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) || in intel_engine_emit_ctx_wa()
1013 IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS) { in intel_engine_emit_ctx_wa()
1021 spin_unlock(&uncore->lock); in intel_engine_emit_ctx_wa()
1022 intel_gt_mcr_unlock(wal->gt, flags); in intel_engine_emit_ctx_wa()
1026 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); in intel_engine_emit_ctx_wa()
1095 /* L3 caching of data atomics doesn't work -- disable it. */ in hsw_gt_workarounds_init()
1110 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in gen9_wa_init_mcr()
1127 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1128 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); in gen9_wa_init_mcr()
1131 subslice--; in gen9_wa_init_mcr()
1140 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); in gen9_wa_init_mcr()
1148 struct drm_i915_private *i915 = gt->i915; in gen9_gt_workarounds_init()
1187 if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) in skl_gt_workarounds_init()
1199 if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) in kbl_gt_workarounds_init()
1251 struct drm_printer p = drm_dbg_printer(>->i915->drm, DRM_UT_DRIVER, in debug_dump_steering()
1263 gt->default_steering.groupid = slice; in __add_mcr_wa()
1264 gt->default_steering.instanceid = subslice; in __add_mcr_wa()
1272 const struct sseu_dev_info *sseu = >->info.sseu; in icl_wa_init_mcr()
1275 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); in icl_wa_init_mcr()
1276 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1292 * worry about explicitly re-steering L3BANK reads later. in icl_wa_init_mcr()
1294 if (gt->info.l3bank_mask & BIT(subslice)) in icl_wa_init_mcr()
1295 gt->steering_table[L3BANK] = NULL; in icl_wa_init_mcr()
1303 const struct sseu_dev_info *sseu = >->info.sseu; in xehp_init_mcr()
1310 * more units that require steering and we're not guaranteed to be able in xehp_init_mcr()
1312 * - GSLICE (fusable) in xehp_init_mcr()
1313 * - DSS (sub-unit within gslice; fusable) in xehp_init_mcr()
1314 * - L3 Bank (fusable) in xehp_init_mcr()
1315 * - MSLICE (fusable) in xehp_init_mcr()
1316 * - LNCF (sub-unit within mslice; always present if mslice is present) in xehp_init_mcr()
1321 * a suitable GSLICE, then we can just re-use the default value and in xehp_init_mcr()
1335 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, in xehp_init_mcr()
1342 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) in xehp_init_mcr()
1351 gt->steering_table[LNCF] = NULL; in xehp_init_mcr()
1355 if (slice_mask & gt->info.mslice_mask) { in xehp_init_mcr()
1356 slice_mask &= gt->info.mslice_mask; in xehp_init_mcr()
1357 gt->steering_table[MSLICE] = NULL; in xehp_init_mcr()
1369 * DG2-G10, any value in the steering registers will work fine since in xehp_init_mcr()
1370 * all instances are present, but DG2-G11 only has SQIDI instances at in xehp_init_mcr()
1382 if (IS_DG2(gt->i915)) in xehp_init_mcr()
1389 struct drm_i915_private *i915 = gt->i915; in icl_gt_workarounds_init()
1453 * Though there are per-engine instances of these registers,
1456 * the engine-specific workaround list.
1465 if (engine->class != VIDEO_DECODE_CLASS || in wa_14011060649()
1466 (engine->instance % 2)) in wa_14011060649()
1469 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), in wa_14011060649()
1479 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ in gen12_gt_workarounds_init()
1482 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ in gen12_gt_workarounds_init()
1520 if (IS_DG2_G10(gt->i915)) { in dg2_gt_workarounds_init()
1587 if (engine->class == VIDEO_DECODE_CLASS) in wa_16021867713()
1588 wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base), in wa_16021867713()
1621 * The bspec performance guide has recommended MMIO tuning settings. These
1623 * workaround infrastructure to make sure they're (re)applied at the proper
1628 * I.e., settings that only need to be re-applied in the event of a full GT
1638 if (IS_DG2(gt->i915)) { in gt_tuning_settings()
1647 struct drm_i915_private *i915 = gt->i915; in gt_init_workarounds()
1651 if (gt->type == GT_MEDIA) { in gt_init_workarounds()
1702 struct i915_wa_list *wal = >->wa_list; in intel_gt_init_workarounds()
1713 if ((cur ^ wa->set) & wa->read) { in wa_verify()
1716 name, from, i915_mmio_reg_offset(wa->reg), in wa_verify()
1717 cur, cur & wa->read, wa->set & wa->read); in wa_verify()
1727 struct intel_gt *gt = wal->gt; in wa_list_apply()
1728 struct intel_uncore *uncore = gt->uncore; in wa_list_apply()
1734 if (!wal->count) in wa_list_apply()
1740 spin_lock(&uncore->lock); in wa_list_apply()
1743 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_apply()
1746 /* open-coded rmw due to steering */ in wa_list_apply()
1747 if (wa->clr) in wa_list_apply()
1748 old = wa->is_mcr ? in wa_list_apply()
1749 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : in wa_list_apply()
1750 intel_uncore_read_fw(uncore, wa->reg); in wa_list_apply()
1751 val = (old & ~wa->clr) | wa->set; in wa_list_apply()
1752 if (val != old || !wa->clr) { in wa_list_apply()
1753 if (wa->is_mcr) in wa_list_apply()
1754 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); in wa_list_apply()
1756 intel_uncore_write_fw(uncore, wa->reg, val); in wa_list_apply()
1760 u32 val = wa->is_mcr ? in wa_list_apply()
1761 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : in wa_list_apply()
1762 intel_uncore_read_fw(uncore, wa->reg); in wa_list_apply()
1764 wa_verify(gt, wa, val, wal->name, "application"); in wa_list_apply()
1769 spin_unlock(&uncore->lock); in wa_list_apply()
1775 wa_list_apply(>->wa_list); in intel_gt_apply_workarounds()
1782 struct intel_uncore *uncore = gt->uncore; in wa_list_verify()
1792 spin_lock(&uncore->lock); in wa_list_verify()
1795 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wa_list_verify()
1796 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? in wa_list_verify()
1797 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : in wa_list_verify()
1798 intel_uncore_read_fw(uncore, wa->reg), in wa_list_verify()
1799 wal->name, from); in wa_list_verify()
1802 spin_unlock(&uncore->lock); in wa_list_verify()
1810 return wa_list_verify(gt, >->wa_list, from); in intel_gt_verify_workarounds()
1835 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) in whitelist_reg_ext()
1853 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) in whitelist_mcr_reg_ext()
1892 struct i915_wa_list *w = &engine->whitelist; in skl_whitelist_build()
1894 if (engine->class != RENDER_CLASS) in skl_whitelist_build()
1905 if (engine->class != RENDER_CLASS) in bxt_whitelist_build()
1908 gen9_whitelist_build(&engine->whitelist); in bxt_whitelist_build()
1913 struct i915_wa_list *w = &engine->whitelist; in kbl_whitelist_build()
1915 if (engine->class != RENDER_CLASS) in kbl_whitelist_build()
1926 struct i915_wa_list *w = &engine->whitelist; in glk_whitelist_build()
1928 if (engine->class != RENDER_CLASS) in glk_whitelist_build()
1939 struct i915_wa_list *w = &engine->whitelist; in cfl_whitelist_build()
1941 if (engine->class != RENDER_CLASS) in cfl_whitelist_build()
1950 * - PS_INVOCATION_COUNT in cfl_whitelist_build()
1951 * - PS_INVOCATION_COUNT_UDW in cfl_whitelist_build()
1952 * - PS_DEPTH_COUNT in cfl_whitelist_build()
1953 * - PS_DEPTH_COUNT_UDW in cfl_whitelist_build()
1962 struct i915_wa_list *w = &engine->whitelist; in allow_read_ctx_timestamp()
1964 if (engine->class != RENDER_CLASS) in allow_read_ctx_timestamp()
1966 RING_CTX_TIMESTAMP(engine->mmio_base), in allow_read_ctx_timestamp()
1979 struct i915_wa_list *w = &engine->whitelist; in icl_whitelist_build()
1983 switch (engine->class) { in icl_whitelist_build()
1998 * - PS_INVOCATION_COUNT in icl_whitelist_build()
1999 * - PS_INVOCATION_COUNT_UDW in icl_whitelist_build()
2000 * - PS_DEPTH_COUNT in icl_whitelist_build()
2001 * - PS_DEPTH_COUNT_UDW in icl_whitelist_build()
2010 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), in icl_whitelist_build()
2013 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), in icl_whitelist_build()
2016 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), in icl_whitelist_build()
2027 struct i915_wa_list *w = &engine->whitelist; in tgl_whitelist_build()
2031 switch (engine->class) { in tgl_whitelist_build()
2038 * - PS_INVOCATION_COUNT in tgl_whitelist_build()
2039 * - PS_INVOCATION_COUNT_UDW in tgl_whitelist_build()
2040 * - PS_DEPTH_COUNT in tgl_whitelist_build()
2041 * - PS_DEPTH_COUNT_UDW in tgl_whitelist_build()
2050 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p in tgl_whitelist_build()
2057 /* Required by recommended tuning setting (not a workaround) */ in tgl_whitelist_build()
2068 struct i915_wa_list *w = &engine->whitelist; in dg2_whitelist_build()
2070 switch (engine->class) { in dg2_whitelist_build()
2072 /* Required by recommended tuning setting (not a workaround) */ in dg2_whitelist_build()
2083 struct i915_wa_list *w = &engine->whitelist; in xelpg_whitelist_build()
2085 switch (engine->class) { in xelpg_whitelist_build()
2087 /* Required by recommended tuning setting (not a workaround) */ in xelpg_whitelist_build()
2098 struct drm_i915_private *i915 = engine->i915; in intel_engine_init_whitelist()
2099 struct i915_wa_list *w = &engine->whitelist; in intel_engine_init_whitelist()
2101 wa_init_start(w, engine->gt, "whitelist", engine->name); in intel_engine_init_whitelist()
2103 if (engine->gt->type == GT_MEDIA) in intel_engine_init_whitelist()
2105 else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) in intel_engine_init_whitelist()
2135 const struct i915_wa_list *wal = &engine->whitelist; in intel_engine_apply_whitelist()
2136 struct intel_uncore *uncore = engine->uncore; in intel_engine_apply_whitelist()
2137 const u32 base = engine->mmio_base; in intel_engine_apply_whitelist()
2141 if (!wal->count) in intel_engine_apply_whitelist()
2144 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in intel_engine_apply_whitelist()
2147 i915_mmio_reg_offset(wa->reg)); in intel_engine_apply_whitelist()
2176 if (GRAPHICS_VER(engine->i915) >= 12) { in engine_fake_wa_init()
2177 mocs_r = engine->gt->mocs.uc_index; in engine_fake_wa_init()
2178 mocs_w = engine->gt->mocs.uc_index; in engine_fake_wa_init()
2180 if (HAS_L3_CCS_READ(engine->i915) && in engine_fake_wa_init()
2181 engine->class == COMPUTE_CLASS) { in engine_fake_wa_init()
2182 mocs_r = engine->gt->mocs.wb_index; in engine_fake_wa_init()
2190 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); in engine_fake_wa_init()
2194 RING_CMD_CCTL(engine->mmio_base), in engine_fake_wa_init()
2203 struct drm_i915_private *i915 = engine->i915; in rcs_engine_wa_init()
2204 struct intel_gt *gt = engine->gt; in rcs_engine_wa_init()
2248 * Wa_1606700617:tgl,dg1,adl-p in rcs_engine_wa_init()
2249 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p in rcs_engine_wa_init()
2250 * Wa_14010826681:tgl,dg1,rkl,adl-p in rcs_engine_wa_init()
2260 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ in rcs_engine_wa_init()
2267 * Wa_14010919138:rkl,dg1,adl-s,adl-p in rcs_engine_wa_init()
2272 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ in rcs_engine_wa_init()
2293 * BSpec; some indicate this is an A0-only WA, others indicate in rcs_engine_wa_init()
2367 * Intel platforms that support fine-grained preemption (i.e., gen9 and in rcs_engine_wa_init()
2368 * beyond) allow the kernel-mode driver to choose between two different in rcs_engine_wa_init()
2373 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity in rcs_engine_wa_init()
2374 * and settings chosen by the kernel-mode driver will apply to all in rcs_engine_wa_init()
2378 * Preemption settings are controlled on a per-context basis via in rcs_engine_wa_init()
2386 * that name is somewhat misleading as other non-granularity in rcs_engine_wa_init()
2392 * userspace developed before object-level preemption was enabled would in rcs_engine_wa_init()
2395 * object-level preemption disabled by default (see in rcs_engine_wa_init()
2397 * userspace drivers could opt-in to object-level preemption as they in rcs_engine_wa_init()
2398 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; in rcs_engine_wa_init()
2405 * - Wa_14015141709: On DG2 and early steppings of MTL, in rcs_engine_wa_init()
2406 * CS_CHICKEN1[0] does not disable object-level preemption as in rcs_engine_wa_init()
2409 * to disable object-level preemption on these platforms/steppings in rcs_engine_wa_init()
2412 * - Wa_16013994831: May require that userspace program in rcs_engine_wa_init()
2671 struct drm_i915_private *i915 = engine->i915; in xcs_engine_wa_init()
2676 RING_SEMA_WAIT_POLL(engine->mmio_base), in xcs_engine_wa_init()
2681 wa_masked_field_set(wal, ECOSKPD(engine->mmio_base), in xcs_engine_wa_init()
2693 * The bspec performance guide has recommended MMIO tuning settings. These
2695 * workaround infrastructure to ensure that they're automatically added to
2696 * the GuC save/restore lists, re-applied at the right times, and checked for
2701 * context, then any tuning settings should be programmed in an appropriate
2708 struct drm_i915_private *i915 = gt->i915; in add_render_compute_tuning_settings()
2714 * This tuning setting proves beneficial only on ATS-M designs; the in add_render_compute_tuning_settings()
2718 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) in add_render_compute_tuning_settings()
2728 struct intel_gt *gt = engine->gt; in ccs_engine_wa_mode()
2731 if (!IS_DG2(gt->i915)) in ccs_engine_wa_mode()
2762 struct drm_i915_private *i915 = engine->i915; in general_render_compute_wa_init()
2763 struct intel_gt *gt = engine->gt; in general_render_compute_wa_init()
2858 * Note that register 0xE420 is write-only and cannot be read in general_render_compute_wa_init()
2864 0 /* write-only, so skip validation */, in general_render_compute_wa_init()
2872 if (GRAPHICS_VER(engine->i915) < 4) in engine_init_workarounds()
2880 * they're reset as part of the general render domain reset. in engine_init_workarounds()
2882 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) { in engine_init_workarounds()
2887 if (engine->class == COMPUTE_CLASS) in engine_init_workarounds()
2889 else if (engine->class == RENDER_CLASS) in engine_init_workarounds()
2897 struct i915_wa_list *wal = &engine->wa_list; in intel_engine_init_workarounds()
2899 wa_init_start(wal, engine->gt, "engine", engine->name); in intel_engine_init_workarounds()
2906 wa_list_apply(&engine->wa_list); in intel_engine_apply_workarounds()
2976 struct drm_i915_private *i915 = rq->i915; in wa_list_srm()
2985 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
2986 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) in wa_list_srm()
2994 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
2995 u32 offset = i915_mmio_reg_offset(wa->reg); in wa_list_srm()
3022 if (!wal->count) in engine_wa_list_verify()
3025 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, in engine_wa_list_verify()
3026 wal->count * sizeof(u32)); in engine_wa_list_verify()
3030 intel_engine_pm_get(ce->engine); in engine_wa_list_verify()
3033 err = i915_gem_object_lock(vma->obj, &ww); in engine_wa_list_verify()
3063 err = -ETIME; in engine_wa_list_verify()
3067 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); in engine_wa_list_verify()
3074 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in engine_wa_list_verify()
3075 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) in engine_wa_list_verify()
3078 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) in engine_wa_list_verify()
3079 err = -ENXIO; in engine_wa_list_verify()
3082 i915_gem_object_unpin_map(vma->obj); in engine_wa_list_verify()
3091 if (err == -EDEADLK) { in engine_wa_list_verify()
3097 intel_engine_pm_put(ce->engine); in engine_wa_list_verify()
3105 return engine_wa_list_verify(engine->kernel_context, in intel_engine_verify_workarounds()
3106 &engine->wa_list, in intel_engine_verify_workarounds()