Lines Matching +full:0 +full:xcfff
133 enum forcewake_domains fw = 0; in wal_get_fw_for_rmw()
137 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wal_get_fw_for_rmw()
150 unsigned int start = 0, end = wal->count; in _wa_add()
206 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
209 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
212 swap(wa_[1], wa_[0]); in _wa_add()
260 wa_write_clr_set(wal, reg, ~0, set); in wa_write()
278 wa_write_clr_set(wal, reg, clr, 0); in wa_write_clr()
284 wa_mcr_write_clr_set(wal, reg, clr, 0); in wa_mcr_write_clr()
301 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
307 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
313 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_masked_dis()
319 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_mcr_masked_dis()
326 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_masked_field_set()
333 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_mcr_masked_field_set()
421 (IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); in bdw_ctx_workarounds_init()
536 u8 vals[3] = { 0, 0, 0 }; in skl_tune_iz_hashing()
539 for (i = 0; i < 3; i++) { in skl_tune_iz_hashing()
550 * subslice_7eu[i] != 0 (because of the check above) and in skl_tune_iz_hashing()
553 * -> 0 <= ss <= 3; in skl_tune_iz_hashing()
559 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) in skl_tune_iz_hashing()
566 GEN9_IZ_HASHING_MASK(0), in skl_tune_iz_hashing()
569 GEN9_IZ_HASHING(0, vals[0])); in skl_tune_iz_hashing()
650 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in icl_ctx_workarounds_init()
652 0 /* write-only, so skip validation */, in icl_ctx_workarounds_init()
665 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); in icl_ctx_workarounds_init()
667 0, in icl_ctx_workarounds_init()
668 0xFFFFFFFF); in icl_ctx_workarounds_init()
683 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
728 * the clear mask is just set to ~0 to make sure other bits are not in gen12_ctx_workarounds_init()
733 ~0, in gen12_ctx_workarounds_init()
735 0, false); in gen12_ctx_workarounds_init()
770 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); in dg2_ctx_workarounds_init()
796 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); in xelpg_ctx_gt_tuning_init()
810 PREEMPTION_VERTEX_COUNT, 0x4000); in xelpg_ctx_workarounds_init()
969 if (wal->count == 0) in intel_engine_emit_ctx_wa()
970 return 0; in intel_engine_emit_ctx_wa()
992 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in intel_engine_emit_ctx_wa()
1015 *cs++ = 0; in intel_engine_emit_ctx_wa()
1016 *cs++ = 0; in intel_engine_emit_ctx_wa()
1030 return 0; in intel_engine_emit_ctx_wa()
1099 HSW_ROW_CHICKEN3, 0, in hsw_gt_workarounds_init()
1101 0 /* XXX does this reg exist? */, true); in hsw_gt_workarounds_init()
1199 if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) in kbl_gt_workarounds_init()
1284 * one of the higher subslices, we run the risk of reading back 0's or in icl_wa_init_mcr()
1287 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); in icl_wa_init_mcr()
1297 __add_mcr_wa(gt, wal, 0, subslice); in icl_wa_init_mcr()
1304 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr()
1305 u32 lncf_mask = 0; in xehp_init_mcr()
1343 lncf_mask |= (0x3 << (i * 2)); in xehp_init_mcr()
1375 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1376 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1383 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); in xehp_init_mcr()
1495 0, 0, false); in gen12_gt_workarounds_init()
1538 0, 0, false); in dg2_gt_workarounds_init()
1652 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) in gt_init_workarounds()
1715 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", in wa_verify()
1743 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_apply()
1744 u32 val, old = 0; in wa_list_apply()
1795 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wa_list_verify()
2010 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), in icl_whitelist_build()
2013 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), in icl_whitelist_build()
2016 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), in icl_whitelist_build()
2144 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in intel_engine_apply_whitelist()
2185 * Even on the few platforms where MOCS 0 is a in engine_fake_wa_init()
2190 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); in engine_fake_wa_init()
2240 wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0, in rcs_engine_wa_init()
2242 0, true); in rcs_engine_wa_init()
2346 0); in rcs_engine_wa_init()
2373 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity in rcs_engine_wa_init()
2379 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on in rcs_engine_wa_init()
2406 * CS_CHICKEN1[0] does not disable object-level preemption as in rcs_engine_wa_init()
2407 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been in rcs_engine_wa_init()
2468 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); in rcs_engine_wa_init()
2470 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); in rcs_engine_wa_init()
2472 EVICTION_PERF_FIX_ENABLE, 0); in rcs_engine_wa_init()
2519 if (0) { /* causes HiZ corruption on ivb:gt1 */ in rcs_engine_wa_init()
2647 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2649 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); in rcs_engine_wa_init()
2663 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
2664 0 /* XXX bit doesn't stick on Broadwater */, in rcs_engine_wa_init()
2858 * Note that register 0xE420 is write-only and cannot be read in general_render_compute_wa_init()
2862 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in general_render_compute_wa_init()
2864 0 /* write-only, so skip validation */, in general_render_compute_wa_init()
2910 { .start = 0x5500, .end = 0x55ff },
2911 { .start = 0x7000, .end = 0x7fff },
2912 { .start = 0x9400, .end = 0x97ff },
2913 { .start = 0xb000, .end = 0xb3ff },
2914 { .start = 0xe000, .end = 0xe7ff },
2919 { .start = 0x8150, .end = 0x815f },
2920 { .start = 0x9520, .end = 0x955f },
2921 { .start = 0xb100, .end = 0xb3ff },
2922 { .start = 0xde80, .end = 0xe8ff },
2923 { .start = 0x24a00, .end = 0x24a7f },
2928 { .start = 0x4000, .end = 0x4aff },
2929 { .start = 0x5200, .end = 0x52ff },
2930 { .start = 0x5400, .end = 0x7fff },
2931 { .start = 0x8140, .end = 0x815f },
2932 { .start = 0x8c80, .end = 0x8dff },
2933 { .start = 0x94d0, .end = 0x955f },
2934 { .start = 0x9680, .end = 0x96ff },
2935 { .start = 0xb000, .end = 0xb3ff },
2936 { .start = 0xc800, .end = 0xcfff },
2937 { .start = 0xd800, .end = 0xd8ff },
2938 { .start = 0xdc00, .end = 0xffff },
2939 { .start = 0x17000, .end = 0x17fff },
2940 { .start = 0x24a00, .end = 0x24a7f },
2963 for (i = 0; mcr_ranges[i].start; i++) in mcr_range()
2977 unsigned int i, count = 0; in wa_list_srm()
2985 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
2994 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
3003 *cs++ = 0; in wa_list_srm()
3007 return 0; in wa_list_srm()
3023 return 0; in engine_wa_list_verify()
3034 if (err == 0) in engine_wa_list_verify()
3039 err = i915_vma_pin_ww(vma, &ww, 0, 0, in engine_wa_list_verify()
3051 if (err == 0) in engine_wa_list_verify()
3062 if (i915_request_wait(rq, 0, HZ / 5) < 0) { in engine_wa_list_verify()
3073 err = 0; in engine_wa_list_verify()
3074 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in engine_wa_list_verify()