Lines Matching full:gating
288 /* TGL only supports slice-level power gating */ in gen12_sseu_info_init()
320 /* ICL has no power gating restrictions. */ in gen11_sseu_info_init()
369 * CHV supports subslice power gating on devices with more than in cherryview_sseu_info_init()
370 * one subslice, and supports EU power gating on devices with in cherryview_sseu_info_init()
454 * SKL+ supports slice power gating on devices with more than in gen9_sseu_info_init()
455 * one slice, and supports EU power gating on devices with in gen9_sseu_info_init()
457 * power gating on devices with more than one subslice, and in gen9_sseu_info_init()
458 * supports EU power gating on devices with more than one EU in gen9_sseu_info_init()
561 * BDW supports slice power gating on devices with more than in bdw_sseu_info_init()
717 * Starting in Gen9, render power gating can leave in intel_sseu_make_rpcs()
800 drm_printf(p, "has slice power gating: %s\n", in intel_sseu_dump()
802 drm_printf(p, "has subslice power gating: %s\n", in intel_sseu_dump()
804 drm_printf(p, "has EU power gating: %s\n", in intel_sseu_dump()