1 // SPDX-License-Identifier: MIT
17 	sseu->max_slices = max_slices;  in intel_sseu_set_info()
18 	sseu->max_subslices = max_subslices;  in intel_sseu_set_info()
19 	sseu->max_eus_per_subslice = max_eus_per_subslice;  in intel_sseu_set_info()
27 	if (sseu->has_xehp_dss)  in intel_sseu_subslice_total()
28 		return bitmap_weight(sseu->subslice_mask.xehp,  in intel_sseu_subslice_total()
29 				     XEHP_BITMAP_BITS(sseu->subslice_mask));  in intel_sseu_subslice_total()
31 	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)  in intel_sseu_subslice_total()
32 		total += hweight8(sseu->subslice_mask.hsw[i]);  in intel_sseu_subslice_total()
40 	WARN_ON(sseu->has_xehp_dss);  in intel_sseu_get_hsw_subslices()
41 	if (WARN_ON(slice >= sseu->max_slices))  in intel_sseu_get_hsw_subslices()
44 	return sseu->subslice_mask.hsw[slice];  in intel_sseu_get_hsw_subslices()
50 	if (sseu->has_xehp_dss) {  in sseu_get_eus()
52 		return sseu->eu_mask.xehp[subslice];  in sseu_get_eus()
54 		return sseu->eu_mask.hsw[slice][subslice];  in sseu_get_eus()
61 	GEM_WARN_ON(eu_mask && __fls(eu_mask) >= sseu->max_eus_per_subslice);  in sseu_set_eus()
62 	if (sseu->has_xehp_dss) {  in sseu_set_eus()
64 		sseu->eu_mask.xehp[subslice] = eu_mask;  in sseu_set_eus()
66 		sseu->eu_mask.hsw[slice][subslice] = eu_mask;  in sseu_set_eus()
74 	for (s = 0; s < sseu->max_slices; s++)  in compute_eu_total()
75 		for (ss = 0; ss < sseu->max_subslices; ss++)  in compute_eu_total()
76 			if (sseu->has_xehp_dss)  in compute_eu_total()
77 				total += hweight16(sseu->eu_mask.xehp[ss]);  in compute_eu_total()
79 				total += hweight16(sseu->eu_mask.hsw[s][ss]);  in compute_eu_total()
85  * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
98 	int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);  in intel_sseu_copy_eumask_to_user()
99 	int len = sseu->max_slices * sseu->max_subslices * eu_stride;  in intel_sseu_copy_eumask_to_user()
102 	for (s = 0; s < sseu->max_slices; s++) {  in intel_sseu_copy_eumask_to_user()
103 		for (ss = 0; ss < sseu->max_subslices; ss++) {  in intel_sseu_copy_eumask_to_user()
105 				s * sseu->max_subslices * eu_stride +  in intel_sseu_copy_eumask_to_user()
119  * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
132 	int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);  in intel_sseu_copy_ssmask_to_user()
133 	int len = sseu->max_slices * ss_stride;  in intel_sseu_copy_ssmask_to_user()
136 	for (s = 0; s < sseu->max_slices; s++) {  in intel_sseu_copy_ssmask_to_user()
137 		for (ss = 0; ss < sseu->max_subslices; ss++) {  in intel_sseu_copy_ssmask_to_user()
153 	u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);  in gen11_compute_sseu_info()
156 	sseu->slice_mask |= BIT(0);  in gen11_compute_sseu_info()
157 	sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;  in gen11_compute_sseu_info()
159 	for (ss = 0; ss < sseu->max_subslices; ss++)  in gen11_compute_sseu_info()
163 	sseu->eu_per_subslice = hweight16(eu_en);  in gen11_compute_sseu_info()
164 	sseu->eu_total = compute_eu_total(sseu);  in gen11_compute_sseu_info()
172 	sseu->slice_mask |= BIT(0);  in xehp_compute_sseu_info()
174 	bitmap_or(sseu->subslice_mask.xehp,  in xehp_compute_sseu_info()
175 		  sseu->compute_subslice_mask.xehp,  in xehp_compute_sseu_info()
176 		  sseu->geometry_subslice_mask.xehp,  in xehp_compute_sseu_info()
177 		  XEHP_BITMAP_BITS(sseu->subslice_mask));  in xehp_compute_sseu_info()
179 	for (ss = 0; ss < sseu->max_subslices; ss++)  in xehp_compute_sseu_info()
183 	sseu->eu_per_subslice = hweight16(eu_en);  in xehp_compute_sseu_info()
184 	sseu->eu_total = compute_eu_total(sseu);  in xehp_compute_sseu_info()
205 	bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);  in xehp_load_dss_mask()
210 	struct sseu_dev_info *sseu = &gt->info.sseu;  in xehp_sseu_info_init()
211 	struct intel_uncore *uncore = gt->uncore;  in xehp_sseu_info_init()
228 			    HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16);  in xehp_sseu_info_init()
229 	sseu->has_xehp_dss = 1;  in xehp_sseu_info_init()
231 	xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,  in xehp_sseu_info_init()
234 	xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask,  in xehp_sseu_info_init()
241 	if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))  in xehp_sseu_info_init()
244 		for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)  in xehp_sseu_info_init()
253 	struct sseu_dev_info *sseu = &gt->info.sseu;  in gen12_sseu_info_init()
254 	struct intel_uncore *uncore = gt->uncore;  in gen12_sseu_info_init()
262 	 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.  in gen12_sseu_info_init()
274 	drm_WARN_ON(&gt->i915->drm, s_en != 0x1);  in gen12_sseu_info_init()
282 	for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)  in gen12_sseu_info_init()
288 	/* TGL only supports slice-level power gating */  in gen12_sseu_info_init()
289 	sseu->has_slice_pg = 1;  in gen12_sseu_info_init()
294 	struct sseu_dev_info *sseu = &gt->info.sseu;  in gen11_sseu_info_init()
295 	struct intel_uncore *uncore = gt->uncore;  in gen11_sseu_info_init()
300 	if (IS_JASPERLAKE(gt->i915) || IS_ELKHARTLAKE(gt->i915))  in gen11_sseu_info_init()
311 	drm_WARN_ON(&gt->i915->drm, s_en != 0x1);  in gen11_sseu_info_init()
321 	sseu->has_slice_pg = 1;  in gen11_sseu_info_init()
322 	sseu->has_subslice_pg = 1;  in gen11_sseu_info_init()
323 	sseu->has_eu_pg = 1;  in gen11_sseu_info_init()
328 	struct sseu_dev_info *sseu = &gt->info.sseu;  in cherryview_sseu_info_init()
329 	u32 fuse;  in cherryview_sseu_info_init()  local
331 	fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);  in cherryview_sseu_info_init()
333 	sseu->slice_mask = BIT(0);  in cherryview_sseu_info_init()
336 	if (!(fuse & CHV_FGT_DISABLE_SS0)) {  in cherryview_sseu_info_init()
338 			((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>  in cherryview_sseu_info_init()
340 			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>  in cherryview_sseu_info_init()
343 		sseu->subslice_mask.hsw[0] |= BIT(0);  in cherryview_sseu_info_init()
347 	if (!(fuse & CHV_FGT_DISABLE_SS1)) {  in cherryview_sseu_info_init()
349 			((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>  in cherryview_sseu_info_init()
351 			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>  in cherryview_sseu_info_init()
354 		sseu->subslice_mask.hsw[0] |= BIT(1);  in cherryview_sseu_info_init()
358 	sseu->eu_total = compute_eu_total(sseu);  in cherryview_sseu_info_init()
364 	sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?  in cherryview_sseu_info_init()
365 		sseu->eu_total /  in cherryview_sseu_info_init()
373 	sseu->has_slice_pg = 0;  in cherryview_sseu_info_init()
374 	sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;  in cherryview_sseu_info_init()
375 	sseu->has_eu_pg = (sseu->eu_per_subslice > 2);  in cherryview_sseu_info_init()
380 	struct drm_i915_private *i915 = gt->i915;  in gen9_sseu_info_init()
381 	struct sseu_dev_info *sseu = &gt->info.sseu;  in gen9_sseu_info_init()
382 	struct intel_uncore *uncore = gt->uncore;  in gen9_sseu_info_init()
388 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;  in gen9_sseu_info_init()
395 	 * The subslice disable field is global, i.e. it applies  in gen9_sseu_info_init()
398 	subslice_mask = (1 << sseu->max_subslices) - 1;  in gen9_sseu_info_init()
406 	for (s = 0; s < sseu->max_slices; s++) {  in gen9_sseu_info_init()
407 		if (!(sseu->slice_mask & BIT(s)))  in gen9_sseu_info_init()
411 		sseu->subslice_mask.hsw[s] = subslice_mask;  in gen9_sseu_info_init()
414 		for (ss = 0; ss < sseu->max_subslices; ss++) {  in gen9_sseu_info_init()
426 			eu_per_ss = sseu->max_eus_per_subslice -  in gen9_sseu_info_init()
435 				sseu->subslice_7eu[s] |= BIT(ss);  in gen9_sseu_info_init()
439 	sseu->eu_total = compute_eu_total(sseu);  in gen9_sseu_info_init()
448 	sseu->eu_per_subslice =  in gen9_sseu_info_init()
450 		DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :  in gen9_sseu_info_init()
461 	sseu->has_slice_pg =  in gen9_sseu_info_init()
462 		!IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;  in gen9_sseu_info_init()
463 	sseu->has_subslice_pg =  in gen9_sseu_info_init()
465 	sseu->has_eu_pg = sseu->eu_per_subslice > 2;  in gen9_sseu_info_init()
468 #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask.hsw[0] & BIT(ss)))  in gen9_sseu_info_init()
469 		RUNTIME_INFO(i915)->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;  in gen9_sseu_info_init()
471 		sseu->min_eu_in_pool = 0;  in gen9_sseu_info_init()
474 				sseu->min_eu_in_pool = 3;  in gen9_sseu_info_init()
476 				sseu->min_eu_in_pool = 6;  in gen9_sseu_info_init()
478 				sseu->min_eu_in_pool = 9;  in gen9_sseu_info_init()
486 	struct sseu_dev_info *sseu = &gt->info.sseu;  in bdw_sseu_info_init()
487 	struct intel_uncore *uncore = gt->uncore;  in bdw_sseu_info_init()
493 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;  in bdw_sseu_info_init()
497 	 * The subslice disable field is global, i.e. it applies  in bdw_sseu_info_init()
500 	subslice_mask = GENMASK(sseu->max_subslices - 1, 0);  in bdw_sseu_info_init()
509 		 (32 - GEN8_EU_DIS0_S1_SHIFT));  in bdw_sseu_info_init()
512 		 (32 - GEN8_EU_DIS1_S2_SHIFT));  in bdw_sseu_info_init()
518 	for (s = 0; s < sseu->max_slices; s++) {  in bdw_sseu_info_init()
519 		if (!(sseu->slice_mask & BIT(s)))  in bdw_sseu_info_init()
523 		sseu->subslice_mask.hsw[s] = subslice_mask;  in bdw_sseu_info_init()
525 		for (ss = 0; ss < sseu->max_subslices; ss++) {  in bdw_sseu_info_init()
534 				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);  in bdw_sseu_info_init()
543 			if (sseu->max_eus_per_subslice - n_disabled == 7)  in bdw_sseu_info_init()
544 				sseu->subslice_7eu[s] |= 1 << ss;  in bdw_sseu_info_init()
548 	sseu->eu_total = compute_eu_total(sseu);  in bdw_sseu_info_init()
555 	sseu->eu_per_subslice =  in bdw_sseu_info_init()
557 		DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :  in bdw_sseu_info_init()
564 	sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;  in bdw_sseu_info_init()
565 	sseu->has_subslice_pg = 0;  in bdw_sseu_info_init()
566 	sseu->has_eu_pg = 0;  in bdw_sseu_info_init()
571 	struct drm_i915_private *i915 = gt->i915;  in hsw_sseu_info_init()
572 	struct sseu_dev_info *sseu = &gt->info.sseu;  in hsw_sseu_info_init()
579 	 * work off the PCI-ids here.  in hsw_sseu_info_init()
581 	switch (INTEL_INFO(i915)->gt) {  in hsw_sseu_info_init()
583 		MISSING_CASE(INTEL_INFO(i915)->gt);  in hsw_sseu_info_init()
586 		sseu->slice_mask = BIT(0);  in hsw_sseu_info_init()
590 		sseu->slice_mask = BIT(0);  in hsw_sseu_info_init()
594 		sseu->slice_mask = BIT(0) | BIT(1);  in hsw_sseu_info_init()
599 	fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);  in hsw_sseu_info_init()
605 		sseu->eu_per_subslice = 10;  in hsw_sseu_info_init()
608 		sseu->eu_per_subslice = 8;  in hsw_sseu_info_init()
611 		sseu->eu_per_subslice = 6;  in hsw_sseu_info_init()
615 	intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),  in hsw_sseu_info_init()
617 			    sseu->eu_per_subslice);  in hsw_sseu_info_init()
619 	for (s = 0; s < sseu->max_slices; s++) {  in hsw_sseu_info_init()
620 		sseu->subslice_mask.hsw[s] = subslice_mask;  in hsw_sseu_info_init()
622 		for (ss = 0; ss < sseu->max_subslices; ss++) {  in hsw_sseu_info_init()
624 				     (1UL << sseu->eu_per_subslice) - 1);  in hsw_sseu_info_init()
628 	sseu->eu_total = compute_eu_total(sseu);  in hsw_sseu_info_init()
631 	sseu->has_slice_pg = 0;  in hsw_sseu_info_init()
632 	sseu->has_subslice_pg = 0;  in hsw_sseu_info_init()
633 	sseu->has_eu_pg = 0;  in hsw_sseu_info_init()
638 	struct drm_i915_private *i915 = gt->i915;  in intel_sseu_info_init()
659 	struct drm_i915_private *i915 = gt->i915;  in intel_sseu_make_rpcs()
660 	const struct sseu_dev_info *sseu = &gt->info.sseu;  in intel_sseu_make_rpcs()
661 	bool subslice_pg = sseu->has_subslice_pg;  in intel_sseu_make_rpcs()
676 	if (gt->perf.group && gt->perf.group[PERF_GROUP_OAG].exclusive_stream)  in intel_sseu_make_rpcs()
677 		req_sseu = &gt->perf.sseu;  in intel_sseu_make_rpcs()
679 	slices = hweight8(req_sseu->slice_mask);  in intel_sseu_make_rpcs()
680 	subslices = hweight8(req_sseu->subslice_mask);  in intel_sseu_make_rpcs()
709 	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {  in intel_sseu_make_rpcs()
722 	if (sseu->has_slice_pg) {  in intel_sseu_make_rpcs()
750 	if (sseu->has_eu_pg) {  in intel_sseu_make_rpcs()
753 		val = req_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;  in intel_sseu_make_rpcs()
759 		val = req_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;  in intel_sseu_make_rpcs()
775 	if (sseu->has_xehp_dss) {  in intel_sseu_dump()
779 			   XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),  in intel_sseu_dump()
780 			   sseu->geometry_subslice_mask.xehp);  in intel_sseu_dump()
782 			   XEHP_BITMAP_BITS(sseu->compute_subslice_mask),  in intel_sseu_dump()
783 			   sseu->compute_subslice_mask.xehp);  in intel_sseu_dump()
786 			   hweight8(sseu->slice_mask), sseu->slice_mask);  in intel_sseu_dump()
790 		for (s = 0; s < sseu->max_slices; s++) {  in intel_sseu_dump()
791 			u8 ss_mask = sseu->subslice_mask.hsw[s];  in intel_sseu_dump()
798 	drm_printf(p, "EU total: %u\n", sseu->eu_total);  in intel_sseu_dump()
799 	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);  in intel_sseu_dump()
801 		   str_yes_no(sseu->has_slice_pg));  in intel_sseu_dump()
803 		   str_yes_no(sseu->has_subslice_pg));  in intel_sseu_dump()
805 		   str_yes_no(sseu->has_eu_pg));  in intel_sseu_dump()
813 	for (s = 0; s < sseu->max_slices; s++) {  in sseu_print_hsw_topology()
814 		u8 ss_mask = sseu->subslice_mask.hsw[s];  in sseu_print_hsw_topology()
819 		for (ss = 0; ss < sseu->max_subslices; ss++) {  in sseu_print_hsw_topology()
833 	for (dss = 0; dss < sseu->max_subslices; dss++) {  in sseu_print_xehp_topology()
837 			   str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),  in sseu_print_xehp_topology()
838 			   str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),  in sseu_print_xehp_topology()
847 	if (sseu->max_slices == 0)  in intel_sseu_print_topology()
861 	if (sseu->has_xehp_dss) {  in intel_sseu_print_ss_info()
863 			   bitmap_weight(sseu->geometry_subslice_mask.xehp,  in intel_sseu_print_ss_info()
864 					 XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));  in intel_sseu_print_ss_info()
866 			   bitmap_weight(sseu->compute_subslice_mask.xehp,  in intel_sseu_print_ss_info()
867 					 XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));  in intel_sseu_print_ss_info()
869 		for (s = 0; s < fls(sseu->slice_mask); s++)  in intel_sseu_print_ss_info()
871 				   s, hweight8(sseu->subslice_mask.hsw[s]));  in intel_sseu_print_ss_info()