Lines Matching +full:cs +full:- +full:x
1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
31 * set-context and then emitting the batch.
41 if (engine->class == RENDER_CLASS) { in set_hwstam()
42 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
56 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
59 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
64 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
67 return sg_page(obj->mm.pages->sgl); in status_page()
84 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
85 switch (engine->id) { in set_hwsp()
91 GEM_BUG_ON(engine->id); in set_hwsp()
106 } else if (GRAPHICS_VER(engine->i915) == 6) { in set_hwsp()
107 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); in set_hwsp()
109 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
112 intel_uncore_write_fw(engine->uncore, hwsp, offset); in set_hwsp()
113 intel_uncore_posting_read_fw(engine->uncore, hwsp); in set_hwsp()
118 if (!IS_GRAPHICS_VER(engine->i915, 6, 7)) in flush_cs_tlb()
123 drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n", in flush_cs_tlb()
124 engine->name); in flush_cs_tlb()
129 if (__intel_wait_for_register_fw(engine->uncore, in flush_cs_tlb()
130 RING_INSTPM(engine->mmio_base), in flush_cs_tlb()
139 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
148 vm = &i915_vm_to_ggtt(vm)->alias->vm; in vm_alias()
155 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir; in pp_dir()
160 struct i915_address_space *vm = vm_alias(engine->gt->vm); in set_pp_dir()
168 if (GRAPHICS_VER(engine->i915) >= 7) { in set_pp_dir()
194 struct intel_ring *ring = engine->legacy.ring; in xcs_resume()
196 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", in xcs_resume()
197 ring->head, ring->tail); in xcs_resume()
203 intel_synchronize_hardirq(engine->i915); in xcs_resume()
207 if (HWS_NEEDS_PHYSICAL(engine->i915)) in xcs_resume()
212 intel_breadcrumbs_reset(engine->breadcrumbs); in xcs_resume()
223 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
226 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); in xcs_resume()
227 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); in xcs_resume()
233 ENGINE_WRITE_FW(engine, RING_HEAD, ring->head); in xcs_resume()
234 ENGINE_WRITE_FW(engine, RING_TAIL, ring->head); in xcs_resume()
238 RING_CTL_SIZE(ring->size) | RING_VALID); in xcs_resume()
241 if (__intel_wait_for_register_fw(engine->uncore, in xcs_resume()
242 RING_CTL(engine->mmio_base), in xcs_resume()
247 if (GRAPHICS_VER(engine->i915) > 2) in xcs_resume()
252 if (ring->tail != ring->head) { in xcs_resume()
253 ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail); in xcs_resume()
262 drm_err(&engine->i915->drm, in xcs_resume()
264 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", in xcs_resume()
265 engine->name, in xcs_resume()
268 ENGINE_READ(engine, RING_HEAD), ring->head, in xcs_resume()
269 ENGINE_READ(engine, RING_TAIL), ring->tail, in xcs_resume()
271 i915_ggtt_offset(ring->vma)); in xcs_resume()
272 return -EIO; in xcs_resume()
279 list_for_each_entry(tl, &engine->status_page.timelines, engine_link) in sanitize_hwsp()
295 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE); in xcs_sanitize()
305 drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); in xcs_sanitize()
334 "{ CTL:%08x, HEAD:%08x, TAIL:%08x, START:%08x }\n", in reset_prepare()
340 drm_err(&engine->i915->drm, in reset_prepare()
342 "ctl %08x head %08x tail %08x start %08x\n", in reset_prepare()
343 engine->name, in reset_prepare()
359 spin_lock_irqsave(&engine->sched_engine->lock, flags); in reset_rewind()
361 list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) { in reset_rewind()
409 GEM_BUG_ON(rq->ring != engine->legacy.ring); in reset_rewind()
410 head = rq->head; in reset_rewind()
412 head = engine->legacy.ring->tail; in reset_rewind()
414 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); in reset_rewind()
416 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in reset_rewind()
428 spin_lock_irqsave(&engine->sched_engine->lock, flags); in reset_cancel()
431 list_for_each_entry(request, &engine->sched_engine->requests, sched.link) in reset_cancel()
437 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in reset_cancel()
445 ENGINE_WRITE(request->engine, RING_TAIL, in i9xx_submit_request()
446 intel_ring_set_tail(request->ring, request->tail)); in i9xx_submit_request()
451 i915_vma_put(ce->state); in __ring_context_fini()
460 if (ce->state) in ring_context_destroy()
470 struct drm_i915_gem_object *obj = ce->state->obj; in ring_context_init_default_state()
477 shmem_read(ce->default_state, 0, vaddr, ce->engine->context_size); in ring_context_init_default_state()
482 __set_bit(CONTEXT_VALID_BIT, &ce->flags); in ring_context_init_default_state()
493 if (ce->default_state && in ring_context_pre_pin()
494 !test_bit(CONTEXT_VALID_BIT, &ce->flags)) { in ring_context_pre_pin()
500 vm = vm_alias(ce->vm); in ring_context_pre_pin()
511 vm = vm_alias(ce->vm); in __context_unpin_ppgtt()
528 struct drm_i915_private *i915 = engine->i915; in alloc_context_vma()
533 obj = i915_gem_object_create_shmem(i915, engine->context_size); in alloc_context_vma()
545 * Snooping is required on non-llc platforms in execlist in alloc_context_vma()
555 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in alloc_context_vma()
570 struct intel_engine_cs *engine = ce->engine; in ring_context_alloc()
573 ce->default_state = engine->default_state; in ring_context_alloc()
576 GEM_BUG_ON(!engine->legacy.ring); in ring_context_alloc()
577 ce->ring = engine->legacy.ring; in ring_context_alloc()
578 ce->timeline = intel_timeline_get(engine->legacy.timeline); in ring_context_alloc()
580 GEM_BUG_ON(ce->state); in ring_context_alloc()
581 if (engine->context_size) { in ring_context_alloc()
588 ce->state = vma; in ring_context_alloc()
601 intel_ring_reset(ce->ring, ce->ring->emit); in ring_context_reset()
602 clear_bit(CONTEXT_VALID_BIT, &ce->flags); in ring_context_reset()
614 engine = rq->engine; in ring_context_revoke()
615 lockdep_assert_held(&engine->sched_engine->lock); in ring_context_revoke()
616 list_for_each_entry_continue(rq, &engine->sched_engine->requests, in ring_context_revoke()
618 if (rq->context == ce) { in ring_context_revoke()
619 i915_request_set_error_once(rq, -EIO); in ring_context_revoke()
632 intel_gt_handle_error(engine->gt, engine->mask, 0, in ring_context_cancel_request()
634 current->comm); in ring_context_cancel_request()
660 const struct intel_engine_cs * const engine = rq->engine; in load_pd_dir()
661 u32 *cs; in load_pd_dir() local
663 cs = intel_ring_begin(rq, 12); in load_pd_dir()
664 if (IS_ERR(cs)) in load_pd_dir()
665 return PTR_ERR(cs); in load_pd_dir()
667 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
668 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
669 *cs++ = valid; in load_pd_dir()
671 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
672 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
673 *cs++ = pp_dir(vm); in load_pd_dir()
676 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; in load_pd_dir()
677 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
678 *cs++ = intel_gt_scratch_offset(engine->gt, in load_pd_dir()
681 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
682 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
683 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
685 intel_ring_advance(rq, cs); in load_pd_dir()
687 return rq->engine->emit_flush(rq, EMIT_FLUSH); in load_pd_dir()
694 struct intel_engine_cs *engine = rq->engine; in mi_set_context()
695 struct drm_i915_private *i915 = engine->i915; in mi_set_context()
698 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; in mi_set_context()
701 u32 *cs; in mi_set_context() local
715 cs = intel_ring_begin(rq, len); in mi_set_context()
716 if (IS_ERR(cs)) in mi_set_context()
717 return PTR_ERR(cs); in mi_set_context()
721 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in mi_set_context()
725 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
726 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
730 *cs++ = i915_mmio_reg_offset( in mi_set_context()
731 RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
732 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
738 * This w/a is only listed for pre-production ilk a/b steppings, in mi_set_context()
741 * this should never take effect and so be a no-op! in mi_set_context()
743 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; in mi_set_context()
759 *cs++ = MI_SET_CONTEXT; in mi_set_context()
760 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
765 *cs++ = MI_NOOP; in mi_set_context()
766 *cs++ = MI_SET_CONTEXT; in mi_set_context()
767 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
772 *cs++ = MI_NOOP; in mi_set_context()
779 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
780 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
784 last_reg = RING_PSMI_CTL(signaller->mmio_base); in mi_set_context()
785 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
786 *cs++ = _MASKED_BIT_DISABLE( in mi_set_context()
791 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; in mi_set_context()
792 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
793 *cs++ = intel_gt_scratch_offset(engine->gt, in mi_set_context()
795 *cs++ = MI_NOOP; in mi_set_context()
797 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in mi_set_context()
799 *cs++ = MI_SUSPEND_FLUSH; in mi_set_context()
802 intel_ring_advance(rq, cs); in mi_set_context()
810 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; in remap_l3_slice() local
816 cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2); in remap_l3_slice()
817 if (IS_ERR(cs)) in remap_l3_slice()
818 return PTR_ERR(cs); in remap_l3_slice()
825 *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW); in remap_l3_slice()
827 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
828 *cs++ = remap_info[i]; in remap_l3_slice()
830 *cs++ = MI_NOOP; in remap_l3_slice()
831 intel_ring_advance(rq, cs); in remap_l3_slice()
842 if (!ctx || !ctx->remap_slice) in remap_l3()
846 if (!(ctx->remap_slice & BIT(i))) in remap_l3()
854 ctx->remap_slice = 0; in remap_l3()
865 ret = rq->engine->emit_flush(rq, EMIT_FLUSH); in switch_mm()
870 * Not only do we need a full barrier (post-sync write) after in switch_mm()
874 * post-sync op, this extra pass appears vital before a in switch_mm()
881 return rq->engine->emit_flush(rq, EMIT_INVALIDATE); in switch_mm()
886 struct intel_engine_cs *engine = rq->engine; in clear_residuals()
889 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm)); in clear_residuals()
893 if (engine->kernel_context->state) { in clear_residuals()
895 engine->kernel_context, in clear_residuals()
901 ret = engine->emit_bb_start(rq, in clear_residuals()
902 i915_vma_offset(engine->wa_ctx.vma), 0, in clear_residuals()
907 ret = engine->emit_flush(rq, EMIT_FLUSH); in clear_residuals()
912 return engine->emit_flush(rq, EMIT_INVALIDATE); in clear_residuals()
917 struct intel_engine_cs *engine = rq->engine; in switch_context()
918 struct intel_context *ce = rq->context; in switch_context()
922 GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); in switch_context()
924 if (engine->wa_ctx.vma && ce != engine->kernel_context) { in switch_context()
925 if (engine->wa_ctx.vma->private != ce && in switch_context()
931 residuals = &engine->wa_ctx.vma->private; in switch_context()
935 ret = switch_mm(rq, vm_alias(ce->vm)); in switch_context()
939 if (ce->state) { in switch_context()
942 GEM_BUG_ON(engine->id != RCS0); in switch_context()
949 if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) in switch_context()
984 GEM_BUG_ON(!intel_context_is_pinned(request->context)); in ring_request_alloc()
985 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb); in ring_request_alloc()
989 * we start building the request - in which case we will just in ring_request_alloc()
992 request->reserved_space += LEGACY_REQUEST_SIZE; in ring_request_alloc()
995 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); in ring_request_alloc()
1003 request->reserved_space -= LEGACY_REQUEST_SIZE; in ring_request_alloc()
1009 struct intel_uncore *uncore = request->engine->uncore; in gen6_bsd_submit_request()
1030 drm_err(&uncore->i915->drm, in gen6_bsd_submit_request()
1047 engine->submit_request = i9xx_submit_request; in i9xx_set_default_submission()
1052 engine->submit_request = gen6_bsd_submit_request; in gen6_bsd_set_default_submission()
1057 struct drm_i915_private *i915 = engine->i915; in ring_release()
1059 drm_WARN_ON(&i915->drm, GRAPHICS_VER(i915) > 2 && in ring_release()
1064 if (engine->wa_ctx.vma) { in ring_release()
1065 intel_context_put(engine->wa_ctx.vma->private); in ring_release()
1066 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); in ring_release()
1069 intel_ring_unpin(engine->legacy.ring); in ring_release()
1070 intel_ring_put(engine->legacy.ring); in ring_release()
1072 intel_timeline_unpin(engine->legacy.timeline); in ring_release()
1073 intel_timeline_put(engine->legacy.timeline); in ring_release()
1083 struct drm_i915_private *i915 = engine->i915; in setup_irq()
1088 engine->irq_enable = gen6_irq_enable; in setup_irq()
1089 engine->irq_disable = gen6_irq_disable; in setup_irq()
1091 engine->irq_enable = gen5_irq_enable; in setup_irq()
1092 engine->irq_disable = gen5_irq_disable; in setup_irq()
1094 engine->irq_enable = gen3_irq_enable; in setup_irq()
1095 engine->irq_disable = gen3_irq_disable; in setup_irq()
1097 engine->irq_enable = gen2_irq_enable; in setup_irq()
1098 engine->irq_disable = gen2_irq_disable; in setup_irq()
1104 lockdep_assert_held(&rq->engine->sched_engine->lock); in add_to_engine()
1105 list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests); in add_to_engine()
1110 spin_lock_irq(&rq->engine->sched_engine->lock); in remove_from_engine()
1111 list_del_init(&rq->sched.link); in remove_from_engine()
1114 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); in remove_from_engine()
1116 spin_unlock_irq(&rq->engine->sched_engine->lock); in remove_from_engine()
1123 struct drm_i915_private *i915 = engine->i915; in setup_common()
1130 engine->resume = xcs_resume; in setup_common()
1131 engine->sanitize = xcs_sanitize; in setup_common()
1133 engine->reset.prepare = reset_prepare; in setup_common()
1134 engine->reset.rewind = reset_rewind; in setup_common()
1135 engine->reset.cancel = reset_cancel; in setup_common()
1136 engine->reset.finish = reset_finish; in setup_common()
1138 engine->add_active_request = add_to_engine; in setup_common()
1139 engine->remove_active_request = remove_from_engine; in setup_common()
1141 engine->cops = &ring_context_ops; in setup_common()
1142 engine->request_alloc = ring_request_alloc; in setup_common()
1147 * engine->emit_init_breadcrumb(). in setup_common()
1149 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; in setup_common()
1151 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; in setup_common()
1153 engine->set_default_submission = i9xx_set_default_submission; in setup_common()
1156 engine->emit_bb_start = gen6_emit_bb_start; in setup_common()
1158 engine->emit_bb_start = gen4_emit_bb_start; in setup_common()
1160 engine->emit_bb_start = i830_emit_bb_start; in setup_common()
1162 engine->emit_bb_start = gen3_emit_bb_start; in setup_common()
1167 struct drm_i915_private *i915 = engine->i915; in setup_rcs()
1170 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in setup_rcs()
1172 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in setup_rcs()
1175 engine->emit_flush = gen7_emit_flush_rcs; in setup_rcs()
1176 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; in setup_rcs()
1178 engine->emit_flush = gen6_emit_flush_rcs; in setup_rcs()
1179 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; in setup_rcs()
1181 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1184 engine->emit_flush = gen2_emit_flush; in setup_rcs()
1186 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1187 engine->irq_enable_mask = I915_USER_INTERRUPT; in setup_rcs()
1191 engine->emit_bb_start = hsw_emit_bb_start; in setup_rcs()
1196 struct drm_i915_private *i915 = engine->i915; in setup_vcs()
1201 engine->set_default_submission = gen6_bsd_set_default_submission; in setup_vcs()
1202 engine->emit_flush = gen6_emit_flush_vcs; in setup_vcs()
1203 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in setup_vcs()
1206 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_vcs()
1208 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vcs()
1210 engine->emit_flush = gen4_emit_flush_vcs; in setup_vcs()
1212 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in setup_vcs()
1214 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in setup_vcs()
1220 struct drm_i915_private *i915 = engine->i915; in setup_bcs()
1222 engine->emit_flush = gen6_emit_flush_xcs; in setup_bcs()
1223 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in setup_bcs()
1226 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_bcs()
1228 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_bcs()
1233 struct drm_i915_private *i915 = engine->i915; in setup_vecs()
1237 engine->emit_flush = gen6_emit_flush_xcs; in setup_vecs()
1238 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in setup_vecs()
1239 engine->irq_enable = hsw_irq_enable_vecs; in setup_vecs()
1240 engine->irq_disable = hsw_irq_disable_vecs; in setup_vecs()
1242 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vecs()
1269 engine->wa_ctx.vma = vma; in gen7_ctx_switch_bb_init()
1283 if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS) in gen7_ctx_vma()
1294 obj = i915_gem_object_create_internal(engine->i915, size); in gen7_ctx_vma()
1298 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in gen7_ctx_vma()
1304 vma->private = intel_context_create(engine); /* dummy residuals */ in gen7_ctx_vma()
1305 if (IS_ERR(vma->private)) { in gen7_ctx_vma()
1306 err = PTR_ERR(vma->private); in gen7_ctx_vma()
1307 vma->private = NULL; in gen7_ctx_vma()
1325 switch (engine->class) { in intel_ring_submission_setup()
1339 MISSING_CASE(engine->class); in intel_ring_submission_setup()
1340 return -ENODEV; in intel_ring_submission_setup()
1349 GEM_BUG_ON(timeline->has_initial_breadcrumb); in intel_ring_submission_setup()
1357 GEM_BUG_ON(engine->legacy.ring); in intel_ring_submission_setup()
1358 engine->legacy.ring = ring; in intel_ring_submission_setup()
1359 engine->legacy.timeline = timeline; in intel_ring_submission_setup()
1370 err = i915_gem_object_lock(timeline->hwsp_ggtt->obj, &ww); in intel_ring_submission_setup()
1372 err = i915_gem_object_lock(gen7_wa_vma->obj, &ww); in intel_ring_submission_setup()
1374 err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww); in intel_ring_submission_setup()
1385 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); in intel_ring_submission_setup()
1396 if (err == -EDEADLK) { in intel_ring_submission_setup()
1406 engine->release = ring_release; in intel_ring_submission_setup()
1412 intel_context_put(gen7_wa_vma->private); in intel_ring_submission_setup()
1413 i915_gem_object_put(gen7_wa_vma->obj); in intel_ring_submission_setup()