Lines Matching full:reset
86 /* Cool contexts are too cool to be banned! (Used for reset testing.) */ in mark_guilty()
93 "%s context reset due to GPU hang\n", in mark_guilty()
165 /* Assert reset for at least 50 usec, and wait for acknowledgement. */ in i915_do_reset()
170 /* Clear the reset request. */ in i915_do_reset()
213 GT_TRACE(gt, "Wait for media reset failed\n"); in g4x_do_reset()
221 GT_TRACE(gt, "Wait for render reset failed\n"); in g4x_do_reset()
247 GT_TRACE(gt, "Wait for render reset failed\n"); in ilk_do_reset()
258 GT_TRACE(gt, "Wait for media reset failed\n"); in ilk_do_reset()
268 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
279 * state is still in flux. If we immediately repeat the reset, the in gen6_hw_domain_reset()
280 * second reset appears to serialise with the first, and since it is a in gen6_hw_domain_reset()
281 * no-op, the registers should retain their reset value. However, there in gen6_hw_domain_reset()
282 * is still a concern that upon leaving the second reset, the internal in gen6_hw_domain_reset()
289 * observed on MTL, we avoid repeating the reset on newer platforms. in gen6_hw_domain_reset()
301 /* Wait for the device to ack the reset requests. */ in gen6_hw_domain_reset()
309 "Wait for 0x%08x engines reset failed\n", in gen6_hw_domain_reset()
463 * If the engine is using an SFC, tell the engine that a software reset in gen11_lock_sfc()
465 * If SFC ends up being locked to the engine we want to reset, we have in gen11_lock_sfc()
466 * to reset it as well (we will unlock it once the reset sequence is in gen11_lock_sfc()
480 * We should reset both the engine and the SFC if: in gen11_lock_sfc()
486 * Otherwise we need only reset the engine by itself and we can in gen11_lock_sfc()
553 * wasn't being reset. So instead of calling gen11_unlock_sfc() in __gen11_reset_engines()
576 * For catastrophic errors, ready-for-reset sequence in gen8_engine_reset_prepare()
597 "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n", in gen8_engine_reset_prepare()
633 * some gens (kbl), possible system hang if reset in gen8_reset_engines()
637 * failed reset with a wedged driver/gpu. And in gen8_reset_engines()
639 * stop_engines() we have before the reset. in gen8_reset_engines()
644 * Wa_22011100796:dg2, whenever Full soft reset is required, in gen8_reset_engines()
645 * reset all individual engines firstly, and then do a full soft reset. in gen8_reset_engines()
647 * This is best effort, so ignore any error from the initial reset. in gen8_reset_engines()
726 * we're going to do a GSC engine reset and then wait for 200ms for the in wa_14015076503_start()
728 * reset attempt and the GSC is not busy, we can try to instead reset in wa_14015076503_start()
746 /* make sure the reset bit is clear when writing the CSR reg */ in wa_14015076503_start()
770 reset_func reset; in __intel_gt_reset() local
774 reset = intel_get_gpu_reset(gt); in __intel_gt_reset()
775 if (!reset) in __intel_gt_reset()
779 * If the power well sleeps during the reset, the reset in __intel_gt_reset()
789 ret = reset(gt, reset_mask, retry); in __intel_gt_reset()
800 if (!gt->i915->params.reset) in intel_has_gpu_reset()
808 if (gt->i915->params.reset < 2) in intel_has_reset_engine()
834 * During the reset sequence, we must prevent the engine from in reset_prepare_engine()
836 * the engine, if it does enter RC6 during the reset, the state in reset_prepare_engine()
838 * GPU state upon resume, i.e. fail to restart after a reset. in reset_prepare_engine()
841 if (engine->reset.prepare) in reset_prepare_engine()
842 engine->reset.prepare(engine); in reset_prepare_engine()
887 * sanitized, do that after engine reset. reset_prepare() in reset_prepare()
888 * is followed by engine reset which in this mode requires GuC to in reset_prepare()
936 if (engine->reset.finish) in reset_finish_engine()
937 engine->reset.finish(engine); in reset_finish_engine()
976 if (test_bit(I915_WEDGED, >->reset.flags)) in __intel_gt_set_wedged()
988 /* Even if the GPU reset fails, it should still stop the engines */ in __intel_gt_set_wedged()
1001 set_bit(I915_WEDGED, >->reset.flags); in __intel_gt_set_wedged()
1006 if (engine->reset.cancel) in __intel_gt_set_wedged()
1007 engine->reset.cancel(engine); in __intel_gt_set_wedged()
1029 if (test_bit(I915_WEDGED, >->reset.flags)) in intel_gt_set_wedged()
1033 mutex_lock(>->reset.mutex); in intel_gt_set_wedged()
1052 mutex_unlock(>->reset.mutex); in intel_gt_set_wedged()
1062 if (!test_bit(I915_WEDGED, >->reset.flags)) in __intel_gt_unset_wedged()
1079 * No more can be submitted until we reset the wedged bit. in __intel_gt_unset_wedged()
1107 /* We must reset pending GPU events before restoring our submission */ in __intel_gt_unset_wedged()
1126 * the nop_submit_request on reset, we can do this from normal in __intel_gt_unset_wedged()
1134 clear_bit(I915_WEDGED, >->reset.flags); in __intel_gt_unset_wedged()
1143 mutex_lock(>->reset.mutex); in intel_gt_unset_wedged()
1145 mutex_unlock(>->reset.mutex); in intel_gt_unset_wedged()
1181 * intel_gt_reset - reset chip after a hang
1182 * @gt: #intel_gt to reset
1186 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1190 * - reset the chip using the reset reg
1204 GT_TRACE(gt, "flags=%lx\n", gt->reset.flags); in intel_gt_reset()
1207 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >->reset.flags)); in intel_gt_reset()
1211 * critical section like gpu reset. in intel_gt_reset()
1215 mutex_lock(>->reset.mutex); in intel_gt_reset()
1228 if (gt->i915->params.reset) in intel_gt_reset()
1229 gt_err(gt, "GPU reset not supported\n"); in intel_gt_reset()
1231 gt_dbg(gt, "GPU reset disabled\n"); in intel_gt_reset()
1239 gt_err(gt, "Failed to reset chip\n"); in intel_gt_reset()
1248 /* sanitize uC after engine reset */ in intel_gt_reset()
1256 * was running at the time of the reset (i.e. we weren't VT in intel_gt_reset()
1261 gt_err(gt, "Failed to initialise HW following reset (%d)\n", ret); in intel_gt_reset()
1272 mutex_unlock(>->reset.mutex); in intel_gt_reset()
1277 * History tells us that if we cannot reset the GPU now, we in intel_gt_reset()
1279 * subsequently. On failing the reset, we mark the driver in intel_gt_reset()
1295 * intel_gt_reset_all_engines() - Reset all engines in the given gt.
1296 * @gt: the GT to reset all engines for.
1309 * intel_gt_reset_engine() - Reset a specific engine within a gt.
1310 * @engine: engine to be reset.
1327 ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags); in __intel_engine_reset_bh()
1328 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags)); in __intel_engine_reset_bh()
1345 /* If we fail here, we expect to fallback to a global reset */ in __intel_engine_reset_bh()
1346 ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret); in __intel_engine_reset_bh()
1359 * have been reset to their default values. Follow the init_ring in __intel_engine_reset_bh()
1372 * intel_engine_reset - reset GPU engine to recover from a hang
1373 * @engine: engine to reset
1374 * @msg: reason for GPU reset; or NULL for no drm_notice()
1376 * Reset a specific GPU engine. Useful if a hang is detected.
1377 * Returns zero on successful reset or otherwise an error code.
1381 * - reset engine (which will force the engine to idle)
1410 /* Use a watchdog to ensure that our reset completes */ in intel_gt_reset_global()
1419 if (!test_bit(I915_WEDGED, >->reset.flags)) in intel_gt_reset_global()
1460 * request that won't finish until the reset is done. This in intel_gt_handle_error()
1462 * simulated reset via debugfs, so get an RPM reference. in intel_gt_handle_error()
1474 * Try engine reset when available. We fall back to full reset if in intel_gt_handle_error()
1475 * single reset fails. in intel_gt_handle_error()
1483 >->reset.flags)) in intel_gt_handle_error()
1490 >->reset.flags); in intel_gt_handle_error()
1498 /* Full reset needs the mutex, stop any other user trying to do so. */ in intel_gt_handle_error()
1499 if (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) { in intel_gt_handle_error()
1500 wait_event(gt->reset.queue, in intel_gt_handle_error()
1501 !test_bit(I915_RESET_BACKOFF, >->reset.flags)); in intel_gt_handle_error()
1502 goto out; /* piggy-back on the other reset */ in intel_gt_handle_error()
1509 * Prevent any other reset-engine attempt. We don't do this for GuC in intel_gt_handle_error()
1510 * submission the GuC owns the per-engine reset, not the i915. in intel_gt_handle_error()
1515 >->reset.flags)) in intel_gt_handle_error()
1516 wait_on_bit(>->reset.flags, in intel_gt_handle_error()
1523 synchronize_srcu_expedited(>->reset.backoff_srcu); in intel_gt_handle_error()
1530 >->reset.flags); in intel_gt_handle_error()
1532 clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags); in intel_gt_handle_error()
1534 wake_up_all(>->reset.queue); in intel_gt_handle_error()
1542 might_lock(>->reset.backoff_srcu); in _intel_gt_reset_lock()
1547 while (test_bit(I915_RESET_BACKOFF, >->reset.flags)) { in _intel_gt_reset_lock()
1553 if (wait_event_interruptible(gt->reset.queue, in _intel_gt_reset_lock()
1555 >->reset.flags))) in _intel_gt_reset_lock()
1560 *srcu = srcu_read_lock(>->reset.backoff_srcu); in _intel_gt_reset_lock()
1577 __releases(>->reset.backoff_srcu) in intel_gt_reset_unlock()
1579 srcu_read_unlock(>->reset.backoff_srcu, tag); in intel_gt_reset_unlock()
1592 /* Reset still in progress? Maybe we will recover? */ in intel_gt_terminally_wedged()
1593 if (wait_event_interruptible(gt->reset.queue, in intel_gt_terminally_wedged()
1595 >->reset.flags))) in intel_gt_terminally_wedged()
1607 set_bit(I915_WEDGED_ON_INIT, >->reset.flags); in intel_gt_set_wedged_on_init()
1617 set_bit(I915_WEDGED_ON_FINI, >->reset.flags); in intel_gt_set_wedged_on_fini()
1623 init_waitqueue_head(>->reset.queue); in intel_gt_init_reset()
1624 mutex_init(>->reset.mutex); in intel_gt_init_reset()
1625 init_srcu_struct(>->reset.backoff_srcu); in intel_gt_init_reset()
1632 * by forcing the reset. Therefore during the reset we must not in intel_gt_init_reset()
1633 * re-enter the shrinker. By declaring that we take the reset mutex in intel_gt_init_reset()
1635 * fs-reclaim or taking related locks during reset. in intel_gt_init_reset()
1637 i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex); in intel_gt_init_reset()
1640 __set_bit(I915_WEDGED, >->reset.flags); in intel_gt_init_reset()
1645 cleanup_srcu_struct(>->reset.backoff_srcu); in intel_gt_fini_reset()
1677 * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.