1 // SPDX-License-Identifier: MIT
24  * low-voltage mode when idle, using down to 0V while at this stage.  This
30  * among each other with the latency required to enter and leave RC6 and
38  * require higher latency to switch to and wake up.
48 	return rc6_to_gt(rc)->uncore;  in rc6_to_uncore()
53 	return rc6_to_gt(rc)->i915;  in rc6_to_i915()
59 	struct intel_uncore *uncore = gt->uncore;  in gen11_rc6_enable()
68 	if (!intel_uc_uses_guc_rc(&gt->uc)) {  in gen11_rc6_enable()
76 			intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);  in gen11_rc6_enable()
88 	 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we  in gen11_rc6_enable()
90 	 * it takes us to service a CS interrupt and submit a new ELSP - that  in gen11_rc6_enable()
93 	 * interrupt service latency, the hardware will automatically gate  in gen11_rc6_enable()
95 	 * the service latency. A similar guide from plane_state is that we  in gen11_rc6_enable()
96 	 * do not want the enable hysteresis to less than the wakeup latency.  in gen11_rc6_enable()
99 	 * service latency, and puts it under 10us for Icelake, similar to  in gen11_rc6_enable()
109 	 * thus allowing GuC to control RC6 entry/exit fully instead.  in gen11_rc6_enable()
113 		rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;  in gen11_rc6_enable()
115 		rc6->ctl_enable =  in gen11_rc6_enable()
121 	 * BSpec 52698 - Render powergating must be off.  in gen11_rc6_enable()
136 	if (GRAPHICS_VER(gt->i915) >= 12) {  in gen11_rc6_enable()
169 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);  in gen9_rc6_enable()
178 	 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we  in gen9_rc6_enable()
180 	 * it takes us to service a CS interrupt and submit a new ELSP - that  in gen9_rc6_enable()
183 	 * interrupt service latency, the hardware will automatically gate  in gen9_rc6_enable()
185 	 * the service latency. A similar guide from plane_state is that we  in gen9_rc6_enable()
186 	 * do not want the enable hysteresis to less than the wakeup latency.  in gen9_rc6_enable()
189 	 * service latency, and puts it around 10us for Broadwell (and other  in gen9_rc6_enable()
190 	 * big core) and around 40us for Broxton (and other low power cores).  in gen9_rc6_enable()
191 	 * [Note that for legacy ringbuffer submission, this is less than 1us!]  in gen9_rc6_enable()
192 	 * However, the wakeup latency on Broxton is closer to 100us. To be  in gen9_rc6_enable()
202 	rc6->ctl_enable =  in gen9_rc6_enable()
209 	 *   - Render/Media PG need to be disabled with RC6.  in gen9_rc6_enable()
227 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);  in gen8_rc6_enable()
229 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */  in gen8_rc6_enable()
232 	rc6->ctl_enable =  in gen8_rc6_enable()
254 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);  in gen6_rc6_enable()
268 	rc6->ctl_enable =  in gen6_rc6_enable()
274 	ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);  in gen6_rc6_enable()
276 		drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");  in gen6_rc6_enable()
279 		drm_dbg(&i915->drm,  in gen6_rc6_enable()
280 			"You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",  in gen6_rc6_enable()
284 		ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);  in gen6_rc6_enable()
286 			drm_err(&i915->drm,  in gen6_rc6_enable()
302 		drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");  in chv_rc6_init()
303 		paddr = i915->dsm.stolen.end + 1 - pctx_size;  in chv_rc6_init()
324 		/* BIOS set it up already, grab the pre-alloc'd space */  in vlv_rc6_init()
327 		pcbr_offset = (pcbr & ~4095) - i915->dsm.stolen.start;  in vlv_rc6_init()
328 		pctx = i915_gem_object_create_region_at(i915->mm.stolen_region,  in vlv_rc6_init()
338 	drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");  in vlv_rc6_init()
350 		drm_dbg(&i915->drm,  in vlv_rc6_init()
356 					 i915->dsm.stolen.start,  in vlv_rc6_init()
357 					 pctx->stolen->start,  in vlv_rc6_init()
359 	pctx_paddr = i915->dsm.stolen.start + pctx->stolen->start;  in vlv_rc6_init()
363 	rc6->pctx = pctx;  in vlv_rc6_init()
379 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);  in chv_rc6_enable()
382 	/* TO threshold set to 500 us (0x186 * 1.28 us) */  in chv_rc6_enable()
392 	rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;  in chv_rc6_enable()
406 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);  in vlv_rc6_enable()
418 	rc6->ctl_enable =  in vlv_rc6_enable()
424 	if (!rc6->bios_state_captured) {  in intel_check_bios_c6_setup()
428 		with_intel_runtime_pm(uncore->rpm, wakeref)  in intel_check_bios_c6_setup()
429 			rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);  in intel_check_bios_c6_setup()
431 		rc6->bios_state_captured = true;  in intel_check_bios_c6_setup()
434 	return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK;  in intel_check_bios_c6_setup()
448 	drm_dbg(&i915->drm, "BIOS enabled RC states: "  in bxt_check_bios_rc6_setup()
455 		drm_dbg(&i915->drm, "RC6 Base location not set properly.\n");  in bxt_check_bios_rc6_setup()
465 	if (!(rc6_ctx_base >= i915->dsm.reserved.start &&  in bxt_check_bios_rc6_setup()
466 	      rc6_ctx_base + PAGE_SIZE < i915->dsm.reserved.end)) {  in bxt_check_bios_rc6_setup()
467 		drm_dbg(&i915->drm, "RC6 Base address not as expected.\n");  in bxt_check_bios_rc6_setup()
475 		drm_dbg(&i915->drm,  in bxt_check_bios_rc6_setup()
483 		drm_dbg(&i915->drm, "Pushbus not setup properly.\n");  in bxt_check_bios_rc6_setup()
488 		drm_dbg(&i915->drm, "GFX pause not setup properly.\n");  in bxt_check_bios_rc6_setup()
493 		drm_dbg(&i915->drm, "GPM control not setup properly.\n");  in bxt_check_bios_rc6_setup()
515 		drm_notice(&i915->drm,  in rc6_supported()
520 	if (IS_METEORLAKE(gt->i915) &&  in rc6_supported()
522 		drm_notice(&i915->drm,  in rc6_supported()
528 		drm_notice(&i915->drm,  in rc6_supported()
538 	GEM_BUG_ON(rc6->wakeref);  in rpm_get()
539 	pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev);  in rpm_get()
540 	rc6->wakeref = true;  in rpm_get()
545 	GEM_BUG_ON(!rc6->wakeref);  in rpm_put()
546 	pm_runtime_put(rc6_to_i915(rc6)->drm.dev);  in rpm_put()
547 	rc6->wakeref = false;  in rpm_put()
560 	drm_notice(&i915->drm,  in pctx_corrupted()
585 		[0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG,  in rc6_res_reg_init()
588 	switch (rc6_to_gt(rc6)->type) {  in rc6_res_reg_init()
600 	memcpy(rc6->res_reg, res_reg, sizeof(res_reg));  in rc6_res_reg_init()
608 	/* Disable runtime-pm until we can save the GPU state with rc6 pctx */  in intel_rc6_init()
626 	rc6->supported = err == 0;  in intel_rc6_init()
631 	memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency));  in intel_rc6_sanitize()
633 	if (rc6->enabled) { /* unbalanced suspend/resume */  in intel_rc6_sanitize()
635 		rc6->enabled = false;  in intel_rc6_sanitize()
638 	if (rc6->supported)  in intel_rc6_sanitize()
647 	if (!rc6->supported)  in intel_rc6_enable()
650 	GEM_BUG_ON(rc6->enabled);  in intel_rc6_enable()
667 	rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;  in intel_rc6_enable()
669 		rc6->ctl_enable = 0;  in intel_rc6_enable()
676 	/* rc6 is ready, runtime-pm is go! */  in intel_rc6_enable()
678 	rc6->enabled = true;  in intel_rc6_enable()
685 	if (!rc6->enabled)  in intel_rc6_unpark()
688 	/* Restore HW timers for automatic RC6 entry while busy */  in intel_rc6_unpark()
689 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);  in intel_rc6_unpark()
697 	if (!rc6->enabled)  in intel_rc6_park()
705 	if (!rc6->manual)  in intel_rc6_park()
722 	if (!rc6->enabled)  in intel_rc6_disable()
726 	rc6->enabled = false;  in intel_rc6_disable()
739 	if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)  in intel_rc6_fini()
740 		intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);  in intel_rc6_fini()
742 	pctx = fetch_and_zero(&rc6->pctx);  in intel_rc6_fini()
746 	if (rc6->wakeref)  in intel_rc6_fini()
759 	lockdep_assert_held(&uncore->lock);  in vlv_residency_raw()
766 	 * Although we always use the counter in high-range mode elsewhere,  in vlv_residency_raw()
784 	} while (upper != tmp && --loop);  in vlv_residency_raw()
788 	 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set  in vlv_residency_raw()
800 	i915_reg_t reg = rc6->res_reg[id];  in intel_rc6_residency_ns()
805 	if (!rc6->supported)  in intel_rc6_residency_ns()
810 	spin_lock_irqsave(&uncore->lock, flags);  in intel_rc6_residency_ns()
813 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */  in intel_rc6_residency_ns()
816 		div = i915->czclk_freq;  in intel_rc6_residency_ns()
820 		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */  in intel_rc6_residency_ns()
836 	 * Store previous hw counter values for counter wrap-around handling. But  in intel_rc6_residency_ns()
839 	prev_hw = rc6->prev_hw_residency[id];  in intel_rc6_residency_ns()
840 	rc6->prev_hw_residency[id] = time_hw;  in intel_rc6_residency_ns()
844 		time_hw -= prev_hw;  in intel_rc6_residency_ns()
846 		time_hw += overflow_hw - prev_hw;  in intel_rc6_residency_ns()
849 	time_hw += rc6->cur_residency[id];  in intel_rc6_residency_ns()
850 	rc6->cur_residency[id] = time_hw;  in intel_rc6_residency_ns()
853 	spin_unlock_irqrestore(&uncore->lock, flags);  in intel_rc6_residency_ns()
866 	struct intel_gt *gt = m->private;  in intel_rc6_print_residency()
867 	i915_reg_t reg = gt->rc6.res_reg[id];  in intel_rc6_print_residency()
870 	with_intel_runtime_pm(gt->uncore->rpm, wakeref)  in intel_rc6_print_residency()
871 		seq_printf(m, "%s %u (%llu us)\n", title,  in intel_rc6_print_residency()
872 			   intel_uncore_read(gt->uncore, reg),  in intel_rc6_print_residency()
873 			   intel_rc6_residency_us(&gt->rc6, id));  in intel_rc6_print_residency()