88 	 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we  in gen11_rc6_enable()
90 	 * it takes us to service a CS interrupt and submit a new ELSP - that  in gen11_rc6_enable()
99 	 * service latency, and puts it under 10us for Icelake, similar to  in gen11_rc6_enable()
178 	 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we  in gen9_rc6_enable()
180 	 * it takes us to service a CS interrupt and submit a new ELSP - that  in gen9_rc6_enable()
189 	 * service latency, and puts it around 10us for Broadwell (and other  in gen9_rc6_enable()
190 	 * big core) and around 40us for Broxton (and other low power cores).  in gen9_rc6_enable()
191 	 * [Note that for legacy ringbuffer submission, this is less than 1us!]  in gen9_rc6_enable()
192 	 * However, the wakeup latency on Broxton is closer to 100us. To be  in gen9_rc6_enable()
223 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);  in gen8_rc6_enable()
229 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */  in gen8_rc6_enable()
248 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);  in gen6_rc6_enable()
374 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);  in chv_rc6_enable()
382 	/* TO threshold set to 500 us (0x186 * 1.28 us) */  in chv_rc6_enable()
762 	 * vlv and chv residency counters are 40 bits in width.  in vlv_residency_raw()
813 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */  in intel_rc6_residency_ns()
817 		overflow_hw = BIT_ULL(40);  in intel_rc6_residency_ns()
820 		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */  in intel_rc6_residency_ns()
871 		seq_printf(m, "%s %u (%llu us)\n", title,  in intel_rc6_print_residency()