i915/gt/intel_mocs.c

74 /* L3 caching options */
109  * PTE and those platforms except TGL/RKL will be initialized L3 WB to
123  *       indices have been set to L3 WB. These reserved entries should never
126  *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
144 	 * - used by the L3 for all of its evictions.
147 	 * - used to force L3 uncachable cycles.
148 	 *   Thus it is expected to make the surface L3 uncacheable.
165 	/* Base - L3 + LLC */ \
173 	/* Base - L3 */ \
185 	/* Age 0 - L3 + LLC */ \
193 	/* Age: Don't Chg. - L3 + LLC */ \
201 	/* No AOM - L3 + LLC */ \
209 	/* No AOM; Age 0 - L3 + LLC */ \
217 	/* No AOM; Age:DC - L3 + LLC */ \
225 	/* Bypass LLC - L3 (Read-Only) (EHL+) */ \
229 	/* Self-Snoop - L3 + LLC */ \
233 	/* Skip Caching - L3 + LLC(12.5%) */ \
237 	/* Skip Caching - L3 + LLC(25%) */ \
241 	/* Skip Caching - L3 + LLC(50%) */ \
245 	/* Skip Caching - L3 + LLC(75%) */ \
249 	/* Skip Caching - L3 + LLC(87.5%) */ \
265 	 * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
277 	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
281 	/* Implicitly enable L1 - HDC:L1 + L3 */
308 	/* Base - L3 + LeCC:PAT (Deprecated) */
320 	/* WB - L3 */
322 	/* WB - L3 50% */
324 	/* WB - L3 25% */
326 	/* WB - L3 12.5% */
329 	/* HDC:L1 + L3 */
343 	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
347 	/* Implicitly enable L1 - HDC:L1 + L3 */
370 	/* UC - Coherent; GO:L3 */
386 	/* Cached - L3 + L4 */
390 	/* L4 - GO:L3 */
394 	/* Uncached - GO:L3 */
406 	/* L4 - L3:NoLKUP; GO:L3 */
410 	/* Uncached - L3:NoLKUP; GO:L3 */
414 	/* L4 - L3:NoLKUP; GO:Mem */
418 	/* Uncached - L3:NoLKUP; GO:Mem */
422 	/* Display - L3; L4:WT */