Lines Matching refs:cs
1045 static u32 *setup_predicate_disable_wa(const struct intel_context *ce, u32 *cs) in setup_predicate_disable_wa() argument
1048 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2); in setup_predicate_disable_wa()
1049 *cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA; in setup_predicate_disable_wa()
1050 *cs++ = 0; in setup_predicate_disable_wa()
1051 *cs++ = 0; /* No predication */ in setup_predicate_disable_wa()
1054 *cs++ = MI_BATCH_BUFFER_END | BIT(15); in setup_predicate_disable_wa()
1055 *cs++ = MI_SET_PREDICATE | MI_SET_PREDICATE_DISABLE; in setup_predicate_disable_wa()
1058 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2); in setup_predicate_disable_wa()
1059 *cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA; in setup_predicate_disable_wa()
1060 *cs++ = 0; in setup_predicate_disable_wa()
1061 *cs++ = 1; /* enable predication before the next BB */ in setup_predicate_disable_wa()
1063 *cs++ = MI_BATCH_BUFFER_END; in setup_predicate_disable_wa()
1064 GEM_BUG_ON(offset_in_page(cs) > DG2_PREDICATE_RESULT_WA); in setup_predicate_disable_wa()
1066 return cs; in setup_predicate_disable_wa()
1258 gen12_emit_timestamp_wa(const struct intel_context *ce, u32 *cs) in gen12_emit_timestamp_wa() argument
1260 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | in gen12_emit_timestamp_wa()
1263 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1264 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_timestamp_wa()
1266 *cs++ = 0; in gen12_emit_timestamp_wa()
1268 *cs++ = MI_LOAD_REGISTER_REG | in gen12_emit_timestamp_wa()
1271 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1272 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1274 *cs++ = MI_LOAD_REGISTER_REG | in gen12_emit_timestamp_wa()
1277 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1278 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1280 return cs; in gen12_emit_timestamp_wa()
1284 gen12_emit_restore_scratch(const struct intel_context *ce, u32 *cs) in gen12_emit_restore_scratch() argument
1288 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | in gen12_emit_restore_scratch()
1291 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_restore_scratch()
1292 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_restore_scratch()
1294 *cs++ = 0; in gen12_emit_restore_scratch()
1296 return cs; in gen12_emit_restore_scratch()
1300 gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs) in gen12_emit_cmd_buf_wa() argument
1304 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | in gen12_emit_cmd_buf_wa()
1307 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1308 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_cmd_buf_wa()
1310 *cs++ = 0; in gen12_emit_cmd_buf_wa()
1312 *cs++ = MI_LOAD_REGISTER_REG | in gen12_emit_cmd_buf_wa()
1315 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1316 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); in gen12_emit_cmd_buf_wa()
1318 return cs; in gen12_emit_cmd_buf_wa()
1329 dg2_emit_draw_watermark_setting(u32 *cs) in dg2_emit_draw_watermark_setting() argument
1331 *cs++ = MI_LOAD_REGISTER_IMM(1); in dg2_emit_draw_watermark_setting()
1332 *cs++ = i915_mmio_reg_offset(DRAW_WATERMARK); in dg2_emit_draw_watermark_setting()
1333 *cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF); in dg2_emit_draw_watermark_setting()
1335 return cs; in dg2_emit_draw_watermark_setting()
1339 gen12_invalidate_state_cache(u32 *cs) in gen12_invalidate_state_cache() argument
1341 *cs++ = MI_LOAD_REGISTER_IMM(1); in gen12_invalidate_state_cache()
1342 *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2); in gen12_invalidate_state_cache()
1343 *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); in gen12_invalidate_state_cache()
1344 return cs; in gen12_invalidate_state_cache()
1348 gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) in gen12_emit_indirect_ctx_rcs() argument
1350 cs = gen12_emit_timestamp_wa(ce, cs); in gen12_emit_indirect_ctx_rcs()
1351 cs = gen12_emit_cmd_buf_wa(ce, cs); in gen12_emit_indirect_ctx_rcs()
1352 cs = gen12_emit_restore_scratch(ce, cs); in gen12_emit_indirect_ctx_rcs()
1356 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); in gen12_emit_indirect_ctx_rcs()
1358 cs = gen12_emit_aux_table_inv(ce->engine, cs); in gen12_emit_indirect_ctx_rcs()
1362 cs = gen12_invalidate_state_cache(cs); in gen12_emit_indirect_ctx_rcs()
1368 cs = dg2_emit_draw_watermark_setting(cs); in gen12_emit_indirect_ctx_rcs()
1370 return cs; in gen12_emit_indirect_ctx_rcs()
1374 gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs) in gen12_emit_indirect_ctx_xcs() argument
1376 cs = gen12_emit_timestamp_wa(ce, cs); in gen12_emit_indirect_ctx_xcs()
1377 cs = gen12_emit_restore_scratch(ce, cs); in gen12_emit_indirect_ctx_xcs()
1382 cs = gen8_emit_pipe_control(cs, in gen12_emit_indirect_ctx_xcs()
1386 return gen12_emit_aux_table_inv(ce->engine, cs); in gen12_emit_indirect_ctx_xcs()
1389 static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs) in xehp_emit_fastcolor_blt_wabb() argument
1413 *cs++ = XY_FAST_COLOR_BLT_CMD | (16 - 2); in xehp_emit_fastcolor_blt_wabb()
1414 *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | 0x3f; in xehp_emit_fastcolor_blt_wabb()
1415 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1416 *cs++ = 4 << 16 | 1; in xehp_emit_fastcolor_blt_wabb()
1417 *cs++ = lower_32_bits(i915_vma_offset(ce->vm->rsvd.vma)); in xehp_emit_fastcolor_blt_wabb()
1418 *cs++ = upper_32_bits(i915_vma_offset(ce->vm->rsvd.vma)); in xehp_emit_fastcolor_blt_wabb()
1419 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1420 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1421 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1422 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1423 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1424 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1425 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1426 *cs++ = 0x20004004; in xehp_emit_fastcolor_blt_wabb()
1427 *cs++ = 0x10; in xehp_emit_fastcolor_blt_wabb()
1428 *cs++ = 0; in xehp_emit_fastcolor_blt_wabb()
1430 return cs; in xehp_emit_fastcolor_blt_wabb()
1434 xehp_emit_per_ctx_bb(const struct intel_context *ce, u32 *cs) in xehp_emit_per_ctx_bb() argument
1438 cs = xehp_emit_fastcolor_blt_wabb(ce, cs); in xehp_emit_per_ctx_bb()
1440 return cs; in xehp_emit_per_ctx_bb()
1450 u32 *cs; in setup_per_ctx_bb() local
1452 cs = emit(ce, start); in setup_per_ctx_bb()
1455 *cs++ = MI_BATCH_BUFFER_END; in setup_per_ctx_bb()
1457 GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); in setup_per_ctx_bb()
1468 u32 *cs; in setup_indirect_ctx_bb() local
1470 cs = emit(ce, start); in setup_indirect_ctx_bb()
1471 GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); in setup_indirect_ctx_bb()
1472 while ((unsigned long)cs % CACHELINE_BYTES) in setup_indirect_ctx_bb()
1473 *cs++ = MI_NOOP; in setup_indirect_ctx_bb()
1475 GEM_BUG_ON(cs - start > DG2_PREDICATE_RESULT_BB / sizeof(*start)); in setup_indirect_ctx_bb()
1480 (cs - start) * sizeof(*cs)); in setup_indirect_ctx_bb()
1557 u32 *(*fn)(const struct intel_context *ce, u32 *cs); in lrc_update_regs()