32  * [5:0]: Number of NOPs or registers to set values to in case of
37  * is used for offsets smaller than 0x200 while the latter is for values bigger
42  * [6:0]: Register offset, without considering the engine base.
53 #define POSTED BIT(0)  in set_offsets()
54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))  in set_offsets()
56 	(((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \  in set_offsets()
57 	(((x) >> 2) & 0x7f)  in set_offsets()
58 #define END 0  in set_offsets()
71 		count = *data & 0x3f;  in set_offsets()
84 			u32 offset = 0;  in set_offsets()
93 			regs[0] = base + (offset << 2);  in set_offsets()
102 			*regs |= BIT(0);  in set_offsets()
108 	LRI(11, 0),
109 	REG16(0x244),
110 	REG(0x034),
111 	REG(0x030),
112 	REG(0x038),
113 	REG(0x03c),
114 	REG(0x168),
115 	REG(0x140),
116 	REG(0x110),
117 	REG(0x11c),
118 	REG(0x114),
119 	REG(0x118),
122 	LRI(9, 0),
123 	REG16(0x3a8),
124 	REG16(0x28c),
125 	REG16(0x288),
126 	REG16(0x284),
127 	REG16(0x280),
128 	REG16(0x27c),
129 	REG16(0x278),
130 	REG16(0x274),
131 	REG16(0x270),
134 	LRI(2, 0),
135 	REG16(0x200),
136 	REG(0x028),
144 	REG16(0x244),
145 	REG(0x034),
146 	REG(0x030),
147 	REG(0x038),
148 	REG(0x03c),
149 	REG(0x168),
150 	REG(0x140),
151 	REG(0x110),
152 	REG(0x11c),
153 	REG(0x114),
154 	REG(0x118),
155 	REG(0x1c0),
156 	REG(0x1c4),
157 	REG(0x1c8),
161 	REG16(0x3a8),
162 	REG16(0x28c),
163 	REG16(0x288),
164 	REG16(0x284),
165 	REG16(0x280),
166 	REG16(0x27c),
167 	REG16(0x278),
168 	REG16(0x274),
169 	REG16(0x270),
173 	REG16(0x200),
177 	REG(0x028),
178 	REG(0x09c),
179 	REG(0x0c0),
180 	REG(0x178),
181 	REG(0x17c),
182 	REG16(0x358),
183 	REG(0x170),
184 	REG(0x150),
185 	REG(0x154),
186 	REG(0x158),
187 	REG16(0x41c),
188 	REG16(0x600),
189 	REG16(0x604),
190 	REG16(0x608),
191 	REG16(0x60c),
192 	REG16(0x610),
193 	REG16(0x614),
194 	REG16(0x618),
195 	REG16(0x61c),
196 	REG16(0x620),
197 	REG16(0x624),
198 	REG16(0x628),
199 	REG16(0x62c),
200 	REG16(0x630),
201 	REG16(0x634),
202 	REG16(0x638),
203 	REG16(0x63c),
204 	REG16(0x640),
205 	REG16(0x644),
206 	REG16(0x648),
207 	REG16(0x64c),
208 	REG16(0x650),
209 	REG16(0x654),
210 	REG16(0x658),
211 	REG16(0x65c),
212 	REG16(0x660),
213 	REG16(0x664),
214 	REG16(0x668),
215 	REG16(0x66c),
216 	REG16(0x670),
217 	REG16(0x674),
218 	REG16(0x678),
219 	REG16(0x67c),
220 	REG(0x068),
228 	REG16(0x244),
229 	REG(0x034),
230 	REG(0x030),
231 	REG(0x038),
232 	REG(0x03c),
233 	REG(0x168),
234 	REG(0x140),
235 	REG(0x110),
236 	REG(0x1c0),
237 	REG(0x1c4),
238 	REG(0x1c8),
239 	REG(0x180),
240 	REG16(0x2b4),
244 	REG16(0x3a8),
245 	REG16(0x28c),
246 	REG16(0x288),
247 	REG16(0x284),
248 	REG16(0x280),
249 	REG16(0x27c),
250 	REG16(0x278),
251 	REG16(0x274),
252 	REG16(0x270),
260 	REG16(0x244),
261 	REG(0x034),
262 	REG(0x030),
263 	REG(0x038),
264 	REG(0x03c),
265 	REG(0x168),
266 	REG(0x140),
267 	REG(0x110),
268 	REG(0x1c0),
269 	REG(0x1c4),
270 	REG(0x1c8),
271 	REG(0x180),
272 	REG16(0x2b4),
273 	REG(0x120),
274 	REG(0x124),
278 	REG16(0x3a8),
279 	REG16(0x28c),
280 	REG16(0x288),
281 	REG16(0x284),
282 	REG16(0x280),
283 	REG16(0x27c),
284 	REG16(0x278),
285 	REG16(0x274),
286 	REG16(0x270),
294 	REG16(0x244),
295 	REG(0x034),
296 	REG(0x030),
297 	REG(0x038),
298 	REG(0x03c),
299 	REG(0x168),
300 	REG(0x140),
301 	REG(0x110),
302 	REG(0x11c),
303 	REG(0x114),
304 	REG(0x118),
305 	REG(0x1c0),
306 	REG(0x1c4),
307 	REG(0x1c8),
311 	REG16(0x3a8),
312 	REG16(0x28c),
313 	REG16(0x288),
314 	REG16(0x284),
315 	REG16(0x280),
316 	REG16(0x27c),
317 	REG16(0x278),
318 	REG16(0x274),
319 	REG16(0x270),
322 	LRI(1, 0),
323 	REG(0x0c8),
331 	REG16(0x244),
332 	REG(0x34),
333 	REG(0x30),
334 	REG(0x38),
335 	REG(0x3c),
336 	REG(0x168),
337 	REG(0x140),
338 	REG(0x110),
339 	REG(0x11c),
340 	REG(0x114),
341 	REG(0x118),
342 	REG(0x1c0),
343 	REG(0x1c4),
344 	REG(0x1c8),
348 	REG16(0x3a8),
349 	REG16(0x28c),
350 	REG16(0x288),
351 	REG16(0x284),
352 	REG16(0x280),
353 	REG16(0x27c),
354 	REG16(0x278),
355 	REG16(0x274),
356 	REG16(0x270),
359 	LRI(1, 0),
360 	REG(0xc8),
364 	REG(0x28),
365 	REG(0x9c),
366 	REG(0xc0),
367 	REG(0x178),
368 	REG(0x17c),
369 	REG16(0x358),
370 	REG(0x170),
371 	REG(0x150),
372 	REG(0x154),
373 	REG(0x158),
374 	REG16(0x41c),
375 	REG16(0x600),
376 	REG16(0x604),
377 	REG16(0x608),
378 	REG16(0x60c),
379 	REG16(0x610),
380 	REG16(0x614),
381 	REG16(0x618),
382 	REG16(0x61c),
383 	REG16(0x620),
384 	REG16(0x624),
385 	REG16(0x628),
386 	REG16(0x62c),
387 	REG16(0x630),
388 	REG16(0x634),
389 	REG16(0x638),
390 	REG16(0x63c),
391 	REG16(0x640),
392 	REG16(0x644),
393 	REG16(0x648),
394 	REG16(0x64c),
395 	REG16(0x650),
396 	REG16(0x654),
397 	REG16(0x658),
398 	REG16(0x65c),
399 	REG16(0x660),
400 	REG16(0x664),
401 	REG16(0x668),
402 	REG16(0x66c),
403 	REG16(0x670),
404 	REG16(0x674),
405 	REG16(0x678),
406 	REG16(0x67c),
407 	REG(0x68),
415 	REG16(0x244),
416 	REG(0x034),
417 	REG(0x030),
418 	REG(0x038),
419 	REG(0x03c),
420 	REG(0x168),
421 	REG(0x140),
422 	REG(0x110),
423 	REG(0x11c),
424 	REG(0x114),
425 	REG(0x118),
426 	REG(0x1c0),
427 	REG(0x1c4),
428 	REG(0x1c8),
429 	REG(0x180),
433 	REG16(0x3a8),
434 	REG16(0x28c),
435 	REG16(0x288),
436 	REG16(0x284),
437 	REG16(0x280),
438 	REG16(0x27c),
439 	REG16(0x278),
440 	REG16(0x274),
441 	REG16(0x270),
444 	REG(0x1b0),
447 	LRI(1, 0),
448 	REG(0x0c8),
456 	REG16(0x244),
457 	REG(0x034),
458 	REG(0x030),
459 	REG(0x038),
460 	REG(0x03c),
461 	REG(0x168),
462 	REG(0x140),
463 	REG(0x110),
464 	REG(0x1c0),
465 	REG(0x1c4),
466 	REG(0x1c8),
467 	REG(0x180),
468 	REG16(0x2b4),
472 	REG16(0x3a8),
473 	REG16(0x28c),
474 	REG16(0x288),
475 	REG16(0x284),
476 	REG16(0x280),
477 	REG16(0x27c),
478 	REG16(0x278),
479 	REG16(0x274),
480 	REG16(0x270),
483 	REG(0x1b0),
484 	REG16(0x5a8),
485 	REG16(0x5ac),
488 	LRI(1, 0),
489 	REG(0x0c8),
493 	REG16(0x588),
494 	REG16(0x588),
495 	REG16(0x588),
496 	REG16(0x588),
497 	REG16(0x588),
498 	REG16(0x588),
499 	REG(0x028),
500 	REG(0x09c),
501 	REG(0x0c0),
502 	REG(0x178),
503 	REG(0x17c),
504 	REG16(0x358),
505 	REG(0x170),
506 	REG(0x150),
507 	REG(0x154),
508 	REG(0x158),
509 	REG16(0x41c),
510 	REG16(0x600),
511 	REG16(0x604),
512 	REG16(0x608),
513 	REG16(0x60c),
514 	REG16(0x610),
515 	REG16(0x614),
516 	REG16(0x618),
517 	REG16(0x61c),
518 	REG16(0x620),
519 	REG16(0x624),
520 	REG16(0x628),
521 	REG16(0x62c),
522 	REG16(0x630),
523 	REG16(0x634),
524 	REG16(0x638),
525 	REG16(0x63c),
526 	REG16(0x640),
527 	REG16(0x644),
528 	REG16(0x648),
529 	REG16(0x64c),
530 	REG16(0x650),
531 	REG16(0x654),
532 	REG16(0x658),
533 	REG16(0x65c),
534 	REG16(0x660),
535 	REG16(0x664),
536 	REG16(0x668),
537 	REG16(0x66c),
538 	REG16(0x670),
539 	REG16(0x674),
540 	REG16(0x678),
541 	REG16(0x67c),
542 	REG(0x068),
543 	REG(0x084),
552 	REG16(0x244),
553 	REG(0x034),
554 	REG(0x030),
555 	REG(0x038),
556 	REG(0x03c),
557 	REG(0x168),
558 	REG(0x140),
559 	REG(0x110),
560 	REG(0x1c0),
561 	REG(0x1c4),
562 	REG(0x1c8),
563 	REG(0x180),
564 	REG16(0x2b4),
565 	REG(0x120),
566 	REG(0x124),
570 	REG16(0x3a8),
571 	REG16(0x28c),
572 	REG16(0x288),
573 	REG16(0x284),
574 	REG16(0x280),
575 	REG16(0x27c),
576 	REG16(0x278),
577 	REG16(0x274),
578 	REG16(0x270),
581 	REG(0x1b0),
582 	REG16(0x5a8),
583 	REG16(0x5ac),
586 	LRI(1, 0),
587 	REG(0x0c8),
595 	REG16(0x244),
596 	REG(0x034),
597 	REG(0x030),
598 	REG(0x038),
599 	REG(0x03c),
600 	REG(0x168),
601 	REG(0x140),
602 	REG(0x110),
603 	REG(0x1c0),
604 	REG(0x1c4),
605 	REG(0x1c8),
606 	REG(0x180),
607 	REG16(0x2b4),
608 	REG(0x120),
609 	REG(0x124),
613 	REG16(0x3a8),
614 	REG16(0x28c),
615 	REG16(0x288),
616 	REG16(0x284),
617 	REG16(0x280),
618 	REG16(0x27c),
619 	REG16(0x278),
620 	REG16(0x274),
621 	REG16(0x270),
625 	REG16(0x5a8),
626 	REG16(0x5ac),
629 	LRI(1, 0),
630 	REG(0x0c8),
680 		return 0x70;  in lrc_ring_mi_mode()
682 		return 0x60;  in lrc_ring_mi_mode()
684 		return 0x54;  in lrc_ring_mi_mode()
686 		return 0x58;  in lrc_ring_mi_mode()
694 		return 0x80;  in lrc_ring_bb_offset()
696 		return 0x70;  in lrc_ring_bb_offset()
698 		return 0x64;  in lrc_ring_bb_offset()
701 		return 0xc4;  in lrc_ring_bb_offset()
709 		return 0x84;  in lrc_ring_gpr0()
711 		return 0x74;  in lrc_ring_gpr0()
713 		return 0x68;  in lrc_ring_gpr0()
715 		return 0xd8;  in lrc_ring_gpr0()
723 		return 0x12;  in lrc_ring_wa_bb_per_ctx()
725 		return 0x18;  in lrc_ring_wa_bb_per_ctx()
735 	if (x < 0)  in lrc_ring_indirect_ptr()
746 	if (x < 0)  in lrc_ring_indirect_offset()
760 		return 0xc6;  in lrc_ring_cmd_buf_cctl()
764 		return 0xb6;  in lrc_ring_cmd_buf_cctl()
766 		return 0xaa;  in lrc_ring_cmd_buf_cctl()
785 	return 0;  in lrc_ring_indirect_offset_default()
861 		regs[loc + 1] = 0;  in init_common_regs()
874 			(ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;  in init_wa_bb_regs()
897 		ASSIGN_CTX_PDP(ppgtt, regs, 0);  in init_ppgtt_regs()
937 		memset(regs, 0, PAGE_SIZE);  in __lrc_init_regs()
1007 	ptr += per_ctx ? PAGE_SIZE : 0;  in context_wabb()
1021 		shmem_read(ce->default_state, 0, state, engine->context_size);  in lrc_init_state()
1027 	memset(state, 0, PAGE_SIZE);  in lrc_init_state()
1031 		memset(state + context_wa_bb_offset(ce), 0, PAGE_SIZE);  in lrc_init_state()
1050 	*cs++ = 0;  in setup_predicate_disable_wa()
1051 	*cs++ = 0; /* No predication */  in setup_predicate_disable_wa()
1053 	/* predicated end, only terminates if SET_PREDICATE_RESULT:0 is clear */  in setup_predicate_disable_wa()
1060 	*cs++ = 0;  in setup_predicate_disable_wa()
1168 	return 0;  in lrc_alloc()
1217 	return 0;  in lrc_pin()
1263 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_timestamp_wa()
1266 	*cs++ = 0;  in gen12_emit_timestamp_wa()
1271 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_timestamp_wa()
1272 	*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));  in gen12_emit_timestamp_wa()
1277 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_timestamp_wa()
1278 	*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));  in gen12_emit_timestamp_wa()
1291 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_restore_scratch()
1294 	*cs++ = 0;  in gen12_emit_restore_scratch()
1307 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_cmd_buf_wa()
1310 	*cs++ = 0;  in gen12_emit_cmd_buf_wa()
1315 	*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));  in gen12_emit_cmd_buf_wa()
1316 	*cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));  in gen12_emit_cmd_buf_wa()
1323  * 0x3FF.  However this register is not saved/restored properly by the
1326  * in this register should remain at 0 (the hardware default).
1333 	*cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF);  in dg2_emit_draw_watermark_setting()
1356 		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);  in gen12_emit_indirect_ctx_rcs()
1361 	if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12, 0), IP_VER(12, 10)))  in gen12_emit_indirect_ctx_rcs()
1384 						    0);  in gen12_emit_indirect_ctx_xcs()
1398 	 * to produce 4 subblits with each subblit generating 0 byte  in xehp_emit_fastcolor_blt_wabb()
1404 	 *  BG2    -> 00000000 (X1, Y1) = (0, 0)  in xehp_emit_fastcolor_blt_wabb()
1414 	*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | 0x3f;  in xehp_emit_fastcolor_blt_wabb()
1415 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1419 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1420 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1421 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1422 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1423 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1424 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1425 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1426 	*cs++ = 0x20004004;  in xehp_emit_fastcolor_blt_wabb()
1427 	*cs++ = 0x10;  in xehp_emit_fastcolor_blt_wabb()
1428 	*cs++ = 0;  in xehp_emit_fastcolor_blt_wabb()
1491  *      bits  0-11:    flags, GEN8_CTX_* (cached in ctx->desc_template)
1495  *      bits 55-63:    group ID, currently unused and set to 0
1642 	*batch++ = 0;  in gen8_emit_flush_coherentl3_wa()
1646 	*batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;  in gen8_emit_flush_coherentl3_wa()
1651 				       0);  in gen8_emit_flush_coherentl3_wa()
1657 	*batch++ = 0;  in gen8_emit_flush_coherentl3_wa()
1736 				       0),  in gen9_init_indirectctx_bb()
1786 		*batch++ = 0x00777000;  in gen9_init_indirectctx_bb()
1787 		*batch++ = 0;  in gen9_init_indirectctx_bb()
1788 		*batch++ = 0;  in gen9_init_indirectctx_bb()
1789 		*batch++ = 0;  in gen9_init_indirectctx_bb()
1820 	return 0;  in lrc_create_wa_ctx()
1829 	i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);  in lrc_fini_wa_ctx()
1851 		wa_bb_fn[0] = gen9_init_indirectctx_bb;  in lrc_init_wa_ctx()
1854 		wa_bb_fn[0] = gen8_init_indirectctx_bb;  in lrc_init_wa_ctx()
1878 		err = i915_ggtt_pin(wa_ctx->vma, &ww, 0, PIN_HIGH);  in lrc_init_wa_ctx()
1894 	for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {  in lrc_init_wa_ctx()
1907 	__i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch);  in lrc_init_wa_ctx()
1929 		memset(wa_ctx, 0, sizeof(*wa_ctx));  in lrc_init_wa_ctx()
1965 	if (unlikely(dt < 0)) {  in lrc_update_runtime()