Lines Matching refs:_MMIO
22 #define PERF_REG(offset) _MMIO(offset)
25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
32 #define RPM_CONFIG0 _MMIO(0xd00)
46 #define RPM_CONFIG1 _MMIO(0xd04)
50 #define RCP_CONFIG _MMIO(0xd08)
52 #define RC6_LOCATION _MMIO(0xd40)
54 #define RC6_CTX_BASE _MMIO(0xd48)
57 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
58 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
59 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
60 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
62 #define FORCEWAKE_ACK_GSC _MMIO(0xdf8)
63 #define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
65 #define GMD_ID_GRAPHICS _MMIO(0xd8c)
66 #define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
68 #define MCFG_MCR_SELECTOR _MMIO(0xfd0)
69 #define MTL_STEER_SEMAPHORE _MMIO(0xfd0)
70 #define MTL_MCR_SELECTOR _MMIO(0xfd4)
71 #define SF_MCR_SELECTOR _MMIO(0xfd8)
72 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
73 #define GAM_MCR_SELECTOR _MMIO(0xfe0)
86 #define IPEIR_I965 _MMIO(0x2064)
87 #define IPEHR_I965 _MMIO(0x2068)
94 #define INSTPS _MMIO(0x2070) /* 965+ only */
95 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
96 #define ACTHD_I965 _MMIO(0x2074)
97 #define HWS_PGA _MMIO(0x2080)
101 #define _3D_CHICKEN _MMIO(0x2084)
104 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
107 #define FF_SLICE_CHICKEN _MMIO(0x2088)
114 #define _3D_CHICKEN2 _MMIO(0x208c)
121 #define _3D_CHICKEN3 _MMIO(0x2090)
129 #define GEN2_INSTDONE _MMIO(0x2090)
130 #define NOPID _MMIO(0x2094)
131 #define HWSTAM _MMIO(0x2098)
133 #define WAIT_FOR_RC6_EXIT _MMIO(0x20cc)
155 #define GEN6_GT_MODE _MMIO(0x20d0)
164 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
167 #define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
170 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
173 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
178 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
180 #define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20ec)
184 #define GEN8_STATE_ACK _MMIO(0x20f0)
185 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20f8)
186 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
195 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
205 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
223 #define CXT_SIZE _MMIO(0x21a0)
232 #define GEN7_CXT_SIZE _MMIO(0x21a8)
242 #define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214)
244 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
247 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
248 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
250 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
251 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
253 #define HS_INVOCATION_COUNT _MMIO(0x2300)
254 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
255 #define DS_INVOCATION_COUNT _MMIO(0x2308)
256 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
257 #define IA_VERTICES_COUNT _MMIO(0x2310)
258 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
259 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
260 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
261 #define VS_INVOCATION_COUNT _MMIO(0x2320)
262 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
263 #define GS_INVOCATION_COUNT _MMIO(0x2328)
264 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
265 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
266 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
267 #define CL_INVOCATION_COUNT _MMIO(0x2338)
268 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
269 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
270 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
271 #define PS_INVOCATION_COUNT _MMIO(0x2348)
272 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
273 #define PS_DEPTH_COUNT _MMIO(0x2350)
274 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
275 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
276 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
277 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
278 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
279 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243c)
280 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
281 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
282 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
283 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
285 #define GFX_MODE _MMIO(0x2520)
287 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
295 #define DRAW_WATERMARK _MMIO(0x26c0)
298 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
300 #define RENDER_HWS_PGA_GEN7 _MMIO(0x4080)
302 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
306 #define GAM_ECOCHK _MMIO(0x4090)
319 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
324 #define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
330 #define ERROR_GEN6 _MMIO(0x40a0)
332 #define DONE_REG _MMIO(0x40b0)
333 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
334 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
335 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
336 #define BSD_HWS_PGA_GEN7 _MMIO(0x4180)
338 #define GEN12_CCS_AUX_INV _MMIO(0x4208)
339 #define GEN12_VD0_AUX_INV _MMIO(0x4218)
340 #define GEN12_VE0_AUX_INV _MMIO(0x4238)
341 #define GEN12_BCS0_AUX_INV _MMIO(0x4248)
343 #define GEN8_RTCR _MMIO(0x4260)
344 #define GEN8_M1TCR _MMIO(0x4264)
345 #define GEN8_M2TCR _MMIO(0x4268)
346 #define GEN8_BTCR _MMIO(0x426c)
347 #define GEN8_VTCR _MMIO(0x4270)
349 #define BLT_HWS_PGA_GEN7 _MMIO(0x4280)
351 #define GEN12_VD2_AUX_INV _MMIO(0x4298)
352 #define GEN12_CCS0_AUX_INV _MMIO(0x42c8)
355 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380)
357 #define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
359 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
361 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
366 #define XELPMP_PAT_INDEX(index) _MMIO(_PAT_INDEX(index))
374 #define GAMTARBMODE _MMIO(0x4a08)
378 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
381 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
386 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
387 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
389 #define GEN11_GACB_PERF_CTRL _MMIO(0x4b80)
395 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
401 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
406 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
407 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
409 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
410 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
412 #define GEN9_WM_CHICKEN3 _MMIO(0x5588)
425 #define GEN12_FF_MODE2 _MMIO(0x6604)
434 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
437 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
443 #define GEN7_GT_MODE _MMIO(0x7008)
448 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
452 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
458 #define HIZ_CHICKEN _MMIO(0x7018)
466 #define GEN8_L3CNTLREG _MMIO(0x7034)
475 #define GEN7_SC_INSTDONE _MMIO(0x7100)
476 #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
477 #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
480 #define HDC_CHICKEN0 _MMIO(0x7300)
488 #define COMMON_SLICE_CHICKEN4 _MMIO(0x7300)
491 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
493 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
500 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
505 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
506 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
512 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
513 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
515 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
516 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
527 #define VF_PREEMPTION _MMIO(0x83a4)
530 #define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
533 #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
535 #define GEN12_SQCNT1 _MMIO(0x8718)
543 #define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
544 #define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
546 #define HSW_IDICR _MMIO(0x9008)
549 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
557 #define VLV_G3DCTL _MMIO(0x9024)
558 #define VLV_GSCKGCTL _MMIO(0x9028)
561 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
564 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
567 #define GEN6_MBCTL _MMIO(0x907c)
575 #define XEHP_FUSE4 _MMIO(0x9114)
577 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
584 #define HSW_PAVP_FUSE1 _MMIO(0x911c)
591 #define GEN8_FUSE2 _MMIO(0x9120)
603 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
604 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
605 #define GEN11_EU_DISABLE _MMIO(0x9134)
610 #define XEHP_EU_ENABLE _MMIO(0x9134)
613 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
618 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
621 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
624 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c)
625 #define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)
627 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
629 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
634 #define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
635 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
637 #define GEN6_UCGCTL1 _MMIO(0x9400)
643 #define GEN6_UCGCTL2 _MMIO(0x9404)
651 #define GEN6_UCGCTL3 _MMIO(0x9408)
654 #define GEN7_UCGCTL4 _MMIO(0x940c)
658 #define GEN6_RCGCTL1 _MMIO(0x9410)
659 #define GEN6_RCGCTL2 _MMIO(0x9414)
661 #define GEN6_GDRST _MMIO(0x941c)
702 #define GEN6_RSTCTL _MMIO(0x9420)
704 #define GEN7_MISCCPCTL _MMIO(0x9424)
711 #define GEN8_UCGCTL6 _MMIO(0x9430)
716 #define UNSLCGCTL9430 _MMIO(0x9430)
719 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
726 #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
735 #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
752 #define MICRO_BP0_0 _MMIO(0x9800)
753 #define MICRO_BP0_2 _MMIO(0x9804)
754 #define MICRO_BP0_1 _MMIO(0x9808)
755 #define MICRO_BP1_0 _MMIO(0x980c)
756 #define MICRO_BP1_2 _MMIO(0x9810)
757 #define MICRO_BP1_1 _MMIO(0x9814)
758 #define MICRO_BP2_0 _MMIO(0x9818)
759 #define MICRO_BP2_2 _MMIO(0x981c)
760 #define MICRO_BP2_1 _MMIO(0x9820)
761 #define MICRO_BP3_0 _MMIO(0x9824)
762 #define MICRO_BP3_2 _MMIO(0x9828)
763 #define MICRO_BP3_1 _MMIO(0x982c)
764 #define MICRO_BP_TRIGGER _MMIO(0x9830)
765 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
766 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
767 #define MICRO_BP_FIRED_ARMED _MMIO(0x983c)
769 #define GEN6_GFXPAUSE _MMIO(0xa000)
770 #define GEN6_RPNSWREQ _MMIO(0xa008)
781 #define GEN6_RC_VIDEO_FREQ _MMIO(0xa00c)
791 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)
792 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)
793 #define GEN6_RPSTAT1 _MMIO(0xa01c)
797 #define GEN6_RP_CONTROL _MMIO(0xa024)
814 #define GEN6_RP_UP_THRESHOLD _MMIO(0xa02c)
815 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xa030)
816 #define GEN6_RP_CUR_UP_EI _MMIO(0xa050)
819 #define GEN6_RP_CUR_UP _MMIO(0xa054)
821 #define GEN6_RP_PREV_UP _MMIO(0xa058)
822 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xa05c)
824 #define GEN6_RP_CUR_DOWN _MMIO(0xa060)
825 #define GEN6_RP_PREV_DOWN _MMIO(0xa064)
826 #define GEN6_RP_UP_EI _MMIO(0xa068)
827 #define GEN6_RP_DOWN_EI _MMIO(0xa06c)
828 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xa070)
829 #define GEN6_RPDEUHWTC _MMIO(0xa080)
830 #define GEN6_RPDEUC _MMIO(0xa084)
831 #define GEN6_RPDEUCSW _MMIO(0xa088)
832 #define GEN6_RC_CONTROL _MMIO(0xa090)
833 #define GEN6_RC_STATE _MMIO(0xa094)
836 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xa098)
837 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xa09c)
838 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xa0a0)
839 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xa0a0)
840 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xa0a8)
841 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xa0ac)
842 #define GEN6_RC_SLEEP _MMIO(0xa0b0)
843 #define GEN6_RCUBMABDTMR _MMIO(0xa0b0)
844 #define GEN6_RC1e_THRESHOLD _MMIO(0xa0b4)
845 #define GEN6_RC6_THRESHOLD _MMIO(0xa0b8)
846 #define GEN6_RC6p_THRESHOLD _MMIO(0xa0bc)
847 #define VLV_RCEDATA _MMIO(0xa0bc)
848 #define GEN6_RC6pp_THRESHOLD _MMIO(0xa0c0)
849 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xa0c4)
850 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xa0c8)
852 #define GEN6_PMINTRMSK _MMIO(0xa168)
856 #define GEN8_MISC_CTRL0 _MMIO(0xa180)
858 #define ECOBUS _MMIO(0xa180)
861 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
862 #define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
863 #define FORCEWAKE _MMIO(0xa18c)
865 #define VLV_SPAREG2H _MMIO(0xa194)
867 #define GEN9_PG_ENABLE _MMIO(0xa210)
874 #define GEN8_PUSHBUS_CONTROL _MMIO(0xa248)
875 #define GEN8_PUSHBUS_ENABLE _MMIO(0xa250)
876 #define GEN8_PUSHBUS_SHIFT _MMIO(0xa25c)
879 #define CTC_MODE _MMIO(0xa26c)
887 #define MSG_IDLE_CS _MMIO(0x8000)
888 #define MSG_IDLE_VCS0 _MMIO(0x8004)
889 #define MSG_IDLE_VCS1 _MMIO(0x8008)
890 #define MSG_IDLE_BCS _MMIO(0x800C)
891 #define MSG_IDLE_VECS0 _MMIO(0x8010)
892 #define MSG_IDLE_VCS2 _MMIO(0x80C0)
893 #define MSG_IDLE_VCS3 _MMIO(0x80C4)
894 #define MSG_IDLE_VCS4 _MMIO(0x80C8)
895 #define MSG_IDLE_VCS5 _MMIO(0x80CC)
896 #define MSG_IDLE_VCS6 _MMIO(0x80D0)
897 #define MSG_IDLE_VCS7 _MMIO(0x80D4)
898 #define MSG_IDLE_VECS1 _MMIO(0x80D8)
899 #define MSG_IDLE_VECS2 _MMIO(0x80DC)
900 #define MSG_IDLE_VECS3 _MMIO(0x80E0)
904 #define RC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
906 #define PWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)
908 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
909 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
911 #define VLV_PWRDWNUPCTL _MMIO(0xa294)
913 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xa2a0)
917 #define MISC_STATUS0 _MMIO(0xa500)
918 #define MISC_STATUS1 _MMIO(0xa504)
920 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
921 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
923 #define FORCEWAKE_REQ_GSC _MMIO(0xa618)
925 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
926 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
927 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
932 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
935 #define GEN7_SARCHKMD _MMIO(0xb000)
939 #define GEN8_GARBCNTL _MMIO(0xb004)
946 #define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
949 #define GEN7_L3SQCREG1 _MMIO(0xb010)
952 #define GEN7_L3CNTLREG1 _MMIO(0xb01c)
956 #define GEN7_L3CNTLREG2 _MMIO(0xb020)
959 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
963 #define GEN7_L3CNTLREG3 _MMIO(0xb024)
965 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xb030)
968 #define GEN7_L3SQCREG4 _MMIO(0xb034)
971 #define HSW_SCRATCH1 _MMIO(0xb038)
974 #define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
1012 #define GEN11_GLBLINVL _MMIO(0xb404)
1016 #define GEN11_LSN_UNSLCVC _MMIO(0xb43c)
1020 #define GUCPMTIMESTAMP _MMIO(0xc3e8)
1023 #define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
1025 #define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
1027 #define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
1029 #define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
1031 #define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
1033 #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
1035 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
1040 #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
1042 #define XELPMP_RING_FAULT_REG _MMIO(0xcec4)
1049 #define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
1051 #define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
1053 #define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
1055 #define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
1057 #define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
1059 #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
1063 #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
1065 #define XELPMP_VDBX_MOD_CTRL _MMIO(0xcf34)
1067 #define XELPMP_VEBX_MOD_CTRL _MMIO(0xcf38)
1079 #define GEN12_GAM_DONE _MMIO(0xcf68)
1081 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
1088 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
1090 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
1096 #define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
1143 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
1157 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
1199 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
1205 #define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
1207 #define CRSTANDVID _MMIO(0x11100)
1208 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1211 #define VIDFREQ_BASE _MMIO(0x11110)
1212 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1213 #define VIDFREQ2 _MMIO(0x11114)
1214 #define VIDFREQ3 _MMIO(0x11118)
1215 #define VIDFREQ4 _MMIO(0x1111c)
1227 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
1236 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
1251 #define MEMIHYST _MMIO(0x1117c)
1252 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
1262 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
1282 #define MEMINTRSTS _MMIO(0x11184)
1291 #define MEMMODECTL _MMIO(0x11190)
1308 #define RCBMAXAVG _MMIO(0x1119c)
1309 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
1321 #define MEMSTAT_CTG _MMIO(0x111a0)
1322 #define RCBMINAVG _MMIO(0x111a0)
1323 #define RCUPEI _MMIO(0x111b0)
1324 #define RCDNEI _MMIO(0x111b4)
1325 #define RSTDBYCTL _MMIO(0x111b8)
1369 #define VIDCTL _MMIO(0x111c0)
1370 #define VIDSTS _MMIO(0x111c8)
1371 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
1372 #define MEMSTAT_ILK _MMIO(0x111f8)
1382 #define PMMISC _MMIO(0x11214)
1384 #define SDEW _MMIO(0x1124c)
1385 #define CSIEW0 _MMIO(0x11250)
1386 #define CSIEW1 _MMIO(0x11254)
1387 #define CSIEW2 _MMIO(0x11258)
1388 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
1389 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
1390 #define MCHAFE _MMIO(0x112c0)
1391 #define CSIEC _MMIO(0x112e0)
1392 #define DMIEC _MMIO(0x112e4)
1393 #define DDREC _MMIO(0x112e8)
1394 #define PEG0EC _MMIO(0x112ec)
1395 #define PEG1EC _MMIO(0x112f0)
1396 #define GFXEC _MMIO(0x112f4)
1397 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
1398 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
1399 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
1400 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
1401 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
1402 #define ECR _MMIO(0x11600)
1406 #define OGW0 _MMIO(0x11608)
1407 #define OGW1 _MMIO(0x1160c)
1408 #define EG0 _MMIO(0x11610)
1409 #define EG1 _MMIO(0x11614)
1410 #define EG2 _MMIO(0x11618)
1411 #define EG3 _MMIO(0x1161c)
1412 #define EG4 _MMIO(0x11620)
1413 #define EG5 _MMIO(0x11624)
1414 #define EG6 _MMIO(0x11628)
1415 #define EG7 _MMIO(0x1162c)
1416 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
1417 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
1418 #define LCFUSE02 _MMIO(0x116c0)
1421 #define GAC_ECO_BITS _MMIO(0x14090)
1426 #define GEN12_RCU_MODE _MMIO(0x14800)
1430 #define XEHP_CCS_MODE _MMIO(0x14804)
1435 #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
1447 #define BCS_SWCTRL _MMIO(0x22200)
1451 #define GAB_CTL _MMIO(0x24000)
1454 #define GEN6_PMISR _MMIO(0x44020)
1455 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
1456 #define GEN6_PMIIR _MMIO(0x44028)
1457 #define GEN6_PMIER _MMIO(0x4402c)
1475 #define GEN7_GT_SCRATCH(i) _MMIO(0x4f100 + (i) * 4)
1478 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
1481 #define GTFIFODBG _MMIO(0x120000)
1492 #define GTFIFOCTL _MMIO(0x120008)
1498 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
1499 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
1500 #define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
1504 #define FORCEWAKE_ACK _MMIO(0x130090)
1505 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
1509 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
1514 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
1517 #define FORCEWAKE_VLV _MMIO(0x1300b0)
1518 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
1519 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
1520 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
1522 #define MTL_MEDIA_MC6 _MMIO(0x138048)
1524 #define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)
1527 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
1530 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
1538 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
1541 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
1542 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
1548 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
1549 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810c)
1551 #define GEN6_GT_GFX_RC6p _MMIO(0x13810c)
1552 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
1553 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
1554 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
1556 #define PCU_PWM_FAN_SPEED _MMIO(0x138140)
1558 #define GEN12_RPSTAT1 _MMIO(0x1381b4)
1562 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
1588 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
1589 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
1590 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
1593 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
1594 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
1595 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
1596 #define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
1598 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
1612 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
1614 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
1615 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
1616 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
1617 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
1618 #define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
1619 #define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
1620 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
1621 #define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
1622 #define GEN12_HECI2_RSVD_INTR_MASK _MMIO(0x1900e4)
1623 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
1624 #define MTL_GUC_MGUC_INTR_MASK _MMIO(0x1900e8) /* MTL+ */
1625 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
1626 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
1627 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
1628 #define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
1629 #define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
1630 #define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
1631 #define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
1632 #define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
1633 #define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
1635 #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)