Lines Matching +full:port +full:- +full:1
1 /* SPDX-License-Identifier: MIT */
14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base)
16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ argument
17 #define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) argument
33 #define STAP_SELECT (1 << 0)
36 #define HS_IO_CTRL_SELECT (1 << 0)
40 #define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTR… argument
42 /* BXT port control */
47 #define DPI_ENABLE (1 << 31) /* A + C */
51 #define DUAL_LINK_MODE_MASK (1 << 26)
53 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
54 #define DITHERING_ENABLE (1 << 25) /* A + C */
55 #define FLOPPED_HSTX (1 << 23)
56 #define DE_INVERT (1 << 19) /* XXX */
59 #define AFE_LATCHOUT (1 << 17)
60 #define LP_OUTPUT_HOLD (1 << 16)
62 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
68 #define CSB_10MHZ (1 << 9)
70 #define BANDGAP_MASK (1 << 8)
72 #define BANDGAP_LNC_CIRCUIT (1 << 8)
75 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
79 #define TEARING_EFFECT_DSI (1 << 2)
84 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
89 #define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_T… argument
93 /* MIPI DSI Controller and D-PHY registers */
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
98 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
99 #define ULPS_STATE_MASK (3 << 1)
100 #define ULPS_STATE_ENTER (2 << 1)
101 #define ULPS_STATE_EXIT (1 << 1)
102 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
103 #define DEVICE_READY (1 << 0)
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
111 #define TEARING_EFFECT (1 << 31)
112 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
113 #define GEN_READ_DATA_AVAIL (1 << 29)
114 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
115 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
116 #define RX_PROT_VIOLATION (1 << 26)
117 #define RX_INVALID_TX_LENGTH (1 << 25)
118 #define ACK_WITH_NO_ERROR (1 << 24)
119 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
120 #define LP_RX_TIMEOUT (1 << 22)
121 #define HS_TX_TIMEOUT (1 << 21)
122 #define DPI_FIFO_UNDERRUN (1 << 20)
123 #define LOW_CONTENTION (1 << 19)
124 #define HIGH_CONTENTION (1 << 18)
125 #define TXDSI_VC_ID_INVALID (1 << 17)
126 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
127 #define TXCHECKSUM_ERROR (1 << 15)
128 #define TXECC_MULTIBIT_ERROR (1 << 14)
129 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
130 #define TXFALSE_CONTROL_ERROR (1 << 12)
131 #define RXDSI_VC_ID_INVALID (1 << 11)
132 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
133 #define RXCHECKSUM_ERROR (1 << 9)
134 #define RXECC_MULTIBIT_ERROR (1 << 8)
135 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
136 #define RXFALSE_CONTROL_ERROR (1 << 6)
137 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
138 #define RX_LP_TX_SYNC_ERROR (1 << 4)
139 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
140 #define RXEOT_SYNC_ERROR (1 << 2)
141 #define RXSOT_SYNC_ERROR (1 << 1)
142 #define RXSOT_ERROR (1 << 0)
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
149 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
156 #define VID_MODE_FORMAT_RGB565 (1 << 7)
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
197 #define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI… argument
199 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
205 #define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_H… argument
209 #define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT,… argument
213 #define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT,… argument
217 #define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HA… argument
221 #define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_V… argument
225 #define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT,… argument
229 #define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT,… argument
233 #define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA… argument
237 #define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONT… argument
238 #define DPI_LP_MODE (1 << 6)
239 #define BACKLIGHT_OFF (1 << 5)
240 #define BACKLIGHT_ON (1 << 4)
241 #define COLOR_MODE_OFF (1 << 3)
242 #define COLOR_MODE_ON (1 << 2)
243 #define TURN_ON (1 << 1)
244 #define SHUTDOWN (1 << 0)
248 #define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _… argument
254 #define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUN… argument
260 #define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_M… argument
266 #define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VID… argument
267 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
268 #define DISABLE_VIDEO_BTA (1 << 3)
269 #define IP_TG_CONFIG (1 << 2)
270 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
276 #define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISA… argument
277 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
278 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
279 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
280 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
281 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
282 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
283 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
284 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
285 #define CLOCKSTOP (1 << 1)
286 #define EOT_DISABLE (1 << 0)
290 #define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECL… argument
296 #define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX… argument
300 #define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_L… argument
305 #define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_D… argument
310 #define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_D… argument
314 #define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_C… argument
317 #define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_C… argument
330 #define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIF… argument
331 #define DPI_FIFO_EMPTY (1 << 28)
332 #define DBI_FIFO_EMPTY (1 << 27)
333 #define LP_CTRL_FIFO_EMPTY (1 << 26)
334 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
335 #define LP_CTRL_FIFO_FULL (1 << 24)
336 #define HS_CTRL_FIFO_EMPTY (1 << 18)
337 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
338 #define HS_CTRL_FIFO_FULL (1 << 16)
339 #define LP_DATA_FIFO_EMPTY (1 << 10)
340 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
341 #define LP_DATA_FIFO_FULL (1 << 8)
342 #define HS_DATA_FIFO_EMPTY (1 << 2)
343 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
344 #define HS_DATA_FIFO_FULL (1 << 0)
348 #define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_L… argument
349 #define DBI_HS_LP_MODE_MASK (1 << 0)
350 #define DBI_LP_MODE (1 << 0)
355 #define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARA… argument
367 #define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_C… argument
371 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MI… argument
379 #define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP… argument
385 #define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_… argument
388 #define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN… argument
389 #define RX_CONTENTION_DETECTED (1 << 0)
393 #define DBI_TYPEC_ENABLE (1 << 31)
394 #define DBI_TYPEC_WIP (1 << 30)
399 #define DBI_TYPEC_OVERRIDE (1 << 8)
407 #define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CT… argument
411 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
417 #define RGB_FLIP_TO_BGR (1 << 2)
422 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
423 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
424 #define GLK_MIPIIO_RESET_RELEASED (1 << 28)
425 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
426 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
427 #define GLK_LP_WAKE (1 << 22)
428 #define GLK_LP11_LOW_PWR_MODE (1 << 21)
429 #define GLK_LP00_LOW_PWR_MODE (1 << 20)
430 #define GLK_FIREWALL_ENABLE (1 << 16)
433 #define BXT_DSC_ENABLE (1 << 3)
434 #define BXT_RGB_FLIP (1 << 2)
435 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
436 #define GLK_MIPIIO_ENABLE (1 << 0)
440 #define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADD… argument
443 #define DATA_VALID (1 << 0)
447 #define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LEN… argument
453 #define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMA… argument
456 #define AUTO_PWG_ENABLE (1 << 2)
457 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
458 #define COMMAND_VALID (1 << 0)
462 #define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAN… argument
468 #define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port… argument
472 #define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_… argument
473 #define READ_DATA_VALID(n) (1 << (n))