220 	const struct intel_bw_state *new_bw_state =  in skl_sagv_pre_plane_update()  local
223 	if (!new_bw_state)  in skl_sagv_pre_plane_update()
226 	if (!intel_can_enable_sagv(i915, new_bw_state))  in skl_sagv_pre_plane_update()
233 	const struct intel_bw_state *new_bw_state =  in skl_sagv_post_plane_update()  local
236 	if (!new_bw_state)  in skl_sagv_post_plane_update()
239 	if (intel_can_enable_sagv(i915, new_bw_state))  in skl_sagv_post_plane_update()
248 	const struct intel_bw_state *new_bw_state =  in icl_sagv_pre_plane_update()  local
252 	if (!new_bw_state)  in icl_sagv_pre_plane_update()
256 	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;  in icl_sagv_pre_plane_update()
261 	WARN_ON(!new_bw_state->base.changed);  in icl_sagv_pre_plane_update()
280 	const struct intel_bw_state *new_bw_state =  in icl_sagv_post_plane_update()  local
284 	if (!new_bw_state)  in icl_sagv_post_plane_update()
287 	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;  in icl_sagv_post_plane_update()
288 	new_mask = new_bw_state->qgv_points_mask;  in icl_sagv_post_plane_update()
293 	WARN_ON(!new_bw_state->base.changed);  in icl_sagv_post_plane_update()
449 	struct intel_bw_state *new_bw_state = NULL;  in intel_compute_sagv_mask()  local
457 		new_bw_state = intel_atomic_get_bw_state(state);  in intel_compute_sagv_mask()
458 		if (IS_ERR(new_bw_state))  in intel_compute_sagv_mask()
459 			return PTR_ERR(new_bw_state);  in intel_compute_sagv_mask()
485 			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);  in intel_compute_sagv_mask()
487 			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);  in intel_compute_sagv_mask()
490 	if (!new_bw_state)  in intel_compute_sagv_mask()
493 	new_bw_state->active_pipes =  in intel_compute_sagv_mask()
496 	if (new_bw_state->active_pipes != old_bw_state->active_pipes) {  in intel_compute_sagv_mask()
497 		ret = intel_atomic_lock_global_state(&new_bw_state->base);  in intel_compute_sagv_mask()
502 	if (intel_can_enable_sagv(i915, new_bw_state) !=  in intel_compute_sagv_mask()
504 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);  in intel_compute_sagv_mask()
507 	} else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {  in intel_compute_sagv_mask()
508 		ret = intel_atomic_lock_global_state(&new_bw_state->base);  in intel_compute_sagv_mask()