607 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state,  in intel_crtc_dbuf_weights()  argument
614 		to_i915(dbuf_state->base.state->base.dev);  in intel_crtc_dbuf_weights()
622 		int weight = dbuf_state->weight[pipe];  in intel_crtc_dbuf_weights()
631 		if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe])  in intel_crtc_dbuf_weights()
1511 	const struct intel_dbuf_state *dbuf_state =  in skl_crtc_allocate_plane_ddb()  local
1513 	const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];  in skl_crtc_allocate_plane_ddb()
1514 	int num_active = hweight8(dbuf_state->active_pipes);  in skl_crtc_allocate_plane_ddb()
2470 static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)  in intel_dbuf_enabled_slices()  argument
2472 	struct drm_i915_private *i915 = to_i915(dbuf_state->base.state->base.dev);  in intel_dbuf_enabled_slices()
2483 		enabled_slices |= dbuf_state->slices[pipe];  in intel_dbuf_enabled_slices()
2974 	struct intel_dbuf_state *dbuf_state =  in skl_wm_get_hw_state()  local
2979 		dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;  in skl_wm_get_hw_state()
2981 	dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915, &i915->display.cdclk.hw);  in skl_wm_get_hw_state()
2997 		memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));  in skl_wm_get_hw_state()
3011 			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);  in skl_wm_get_hw_state()
3012 			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);  in skl_wm_get_hw_state()
3015 		dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);  in skl_wm_get_hw_state()
3021 		slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,  in skl_wm_get_hw_state()
3022 						 dbuf_state->joined_mbus);  in skl_wm_get_hw_state()
3024 		crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;  in skl_wm_get_hw_state()
3025 		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;  in skl_wm_get_hw_state()
3028 		dbuf_state->slices[pipe] =  in skl_wm_get_hw_state()
3034 			    dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,  in skl_wm_get_hw_state()
3035 			    dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,  in skl_wm_get_hw_state()
3036 			    str_yes_no(dbuf_state->joined_mbus));  in skl_wm_get_hw_state()
3039 	dbuf_state->enabled_slices = i915->display.dbuf.enabled_slices;  in skl_wm_get_hw_state()
3044 	const struct intel_dbuf_state *dbuf_state =  in skl_dbuf_is_misconfigured()  local
3061 		slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,  in skl_dbuf_is_misconfigured()
3062 						 dbuf_state->joined_mbus);  in skl_dbuf_is_misconfigured()
3063 		if (dbuf_state->slices[crtc->pipe] & ~slices)  in skl_dbuf_is_misconfigured()
3409 	struct intel_dbuf_state *dbuf_state;  in intel_dbuf_duplicate_state()  local
3411 	dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL);  in intel_dbuf_duplicate_state()
3412 	if (!dbuf_state)  in intel_dbuf_duplicate_state()
3415 	return &dbuf_state->base;  in intel_dbuf_duplicate_state()
3433 	struct intel_global_state *dbuf_state;  in intel_atomic_get_dbuf_state()  local
3435 	dbuf_state = intel_atomic_get_global_obj_state(state, &i915->display.dbuf.obj);  in intel_atomic_get_dbuf_state()
3436 	if (IS_ERR(dbuf_state))  in intel_atomic_get_dbuf_state()
3437 		return ERR_CAST(dbuf_state);  in intel_atomic_get_dbuf_state()
3439 	return to_intel_dbuf_state(dbuf_state);  in intel_atomic_get_dbuf_state()
3444 	struct intel_dbuf_state *dbuf_state;  in intel_dbuf_init()  local
3446 	dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);  in intel_dbuf_init()
3447 	if (!dbuf_state)  in intel_dbuf_init()
3451 				     &dbuf_state->base, &intel_dbuf_funcs);  in intel_dbuf_init()
3542 	struct intel_dbuf_state *dbuf_state;  in intel_dbuf_state_set_mdclk_cdclk_ratio()  local
3544 	dbuf_state = intel_atomic_get_dbuf_state(state);  in intel_dbuf_state_set_mdclk_cdclk_ratio()
3545 	if (IS_ERR(dbuf_state))  in intel_dbuf_state_set_mdclk_cdclk_ratio()
3546 		return PTR_ERR(dbuf_state);  in intel_dbuf_state_set_mdclk_cdclk_ratio()
3548 	dbuf_state->mdclk_cdclk_ratio = ratio;  in intel_dbuf_state_set_mdclk_cdclk_ratio()
3550 	return intel_atomic_lock_global_state(&dbuf_state->base);  in intel_dbuf_state_set_mdclk_cdclk_ratio()
3599 					const struct intel_dbuf_state *dbuf_state)  in intel_mbus_joined_pipe()  argument
3602 	enum pipe pipe = ffs(dbuf_state->active_pipes) - 1;  in intel_mbus_joined_pipe()
3606 	drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);  in intel_mbus_joined_pipe()
3607 	drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));  in intel_mbus_joined_pipe()