Lines Matching +full:offset +full:- +full:y
1 // SPDX-License-Identifier: MIT
278 const struct drm_framebuffer *fb = plane_state->hw.fb; in glk_plane_ratio()
280 if (fb->format->cpp[0] == 8) { in glk_plane_ratio()
305 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_ratio()
307 if (fb->format->cpp[0] == 8) { in skl_plane_ratio()
331 int cpp = fb->format->cpp[color_plane]; in skl_plane_max_width()
333 switch (fb->modifier) { in skl_plane_max_width()
339 * - Ytile (already limited to 4k) in skl_plane_max_width()
340 * - FP16 (already limited to 4k) in skl_plane_max_width()
341 * - render compression (already limited to 4k) in skl_plane_max_width()
342 * - KVMR sprite and cursor (don't care) in skl_plane_max_width()
343 * - horizontal panning (TODO verify this) in skl_plane_max_width()
344 * - pipe and plane scaling (TODO verify this) in skl_plane_max_width()
361 MISSING_CASE(fb->modifier); in skl_plane_max_width()
370 int cpp = fb->format->cpp[color_plane]; in glk_plane_max_width()
372 switch (fb->modifier) { in glk_plane_max_width()
389 MISSING_CASE(fb->modifier); in glk_plane_max_width()
399 switch (fb->format->format) { in icl_plane_min_width()
438 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) in icl_hdr_plane_max_width()
473 int cpp = info->cpp[0]; in plane_max_stride()
511 struct drm_i915_private *i915 = to_i915(plane->base.dev); in tgl_plane_min_alignment()
512 /* PLANE_SURF GGTT -> DPT alignment */ in tgl_plane_min_alignment()
519 switch (fb->modifier) { in tgl_plane_min_alignment()
549 MISSING_CASE(fb->modifier); in tgl_plane_min_alignment()
565 switch (fb->modifier) { in skl_plane_min_alignment()
575 MISSING_CASE(fb->modifier); in skl_plane_min_alignment()
593 * in full-range YCbCr.
600 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in icl_program_input_csc()
601 enum pipe pipe = plane->pipe; in icl_program_input_csc()
602 enum plane_id plane_id = plane->id; in icl_program_input_csc()
606 * BT.601 full range YCbCr -> full range RGB in icl_program_input_csc()
609 * 1.000, -0.336, -0.698, in icl_program_input_csc()
618 * BT.709 full range YCbCr -> full range RGB in icl_program_input_csc()
621 * 1.000, -0.187, -0.468, in icl_program_input_csc()
630 * BT.2020 full range YCbCr -> full range RGB in icl_program_input_csc()
633 * 1.000, -0.1645, -0.5713, in icl_program_input_csc()
642 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; in icl_program_input_csc()
689 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_stride()
690 unsigned int rotation = plane_state->hw.rotation; in skl_plane_stride()
691 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride; in skl_plane_stride()
693 if (color_plane >= fb->format->num_planes) in skl_plane_stride()
701 if (!entry->end) in skl_plane_ddb_reg_val()
704 return PLANE_BUF_END(entry->end - 1) | in skl_plane_ddb_reg_val()
705 PLANE_BUF_START(entry->start); in skl_plane_ddb_reg_val()
712 if (level->enable) in skl_plane_wm_reg_val()
714 if (level->ignore_lines) in skl_plane_wm_reg_val()
716 val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); in skl_plane_wm_reg_val()
717 val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); in skl_plane_wm_reg_val()
725 struct drm_i915_private *i915 = to_i915(plane->base.dev); in skl_write_plane_wm()
726 enum plane_id plane_id = plane->id; in skl_write_plane_wm()
727 enum pipe pipe = plane->pipe; in skl_write_plane_wm()
728 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_plane_wm()
730 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_plane_wm()
732 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
735 for (level = 0; level < i915->display.wm.num_levels; level++) in skl_write_plane_wm()
743 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_plane_wm()
746 skl_plane_wm_reg_val(&wm->sagv.wm0)); in skl_write_plane_wm()
748 skl_plane_wm_reg_val(&wm->sagv.trans_wm)); in skl_write_plane_wm()
763 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_plane_disable_arm()
764 enum plane_id plane_id = plane->id; in skl_plane_disable_arm()
765 enum pipe pipe = plane->pipe; in skl_plane_disable_arm()
776 struct drm_i915_private *i915 = to_i915(plane->base.dev); in icl_plane_disable_sel_fetch_arm()
777 enum pipe pipe = plane->pipe; in icl_plane_disable_sel_fetch_arm()
779 if (!crtc_state->enable_psr2_sel_fetch) in icl_plane_disable_sel_fetch_arm()
782 intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); in icl_plane_disable_sel_fetch_arm()
789 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in icl_plane_disable_arm()
790 enum plane_id plane_id = plane->id; in icl_plane_disable_arm()
791 enum pipe pipe = plane->pipe; in icl_plane_disable_arm()
807 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_plane_get_hw_state()
809 enum plane_id plane_id = plane->id; in skl_plane_get_hw_state()
813 power_domain = POWER_DOMAIN_PIPE(plane->pipe); in skl_plane_get_hw_state()
818 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; in skl_plane_get_hw_state()
820 *pipe = plane->pipe; in skl_plane_get_hw_state()
891 if (!plane_state->hw.fb->format->has_alpha) in skl_plane_ctl_alpha()
894 switch (plane_state->hw.pixel_blend_mode) { in skl_plane_ctl_alpha()
902 MISSING_CASE(plane_state->hw.pixel_blend_mode); in skl_plane_ctl_alpha()
909 if (!plane_state->hw.fb->format->has_alpha) in glk_plane_color_ctl_alpha()
912 switch (plane_state->hw.pixel_blend_mode) { in glk_plane_color_ctl_alpha()
920 MISSING_CASE(plane_state->hw.pixel_blend_mode); in glk_plane_color_ctl_alpha()
1016 const struct drm_framebuffer *fb = plane_state->hw.fb; in adlp_plane_ctl_arb_slots()
1018 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { in adlp_plane_ctl_arb_slots()
1019 switch (fb->format->cpp[0]) { in adlp_plane_ctl_arb_slots()
1026 switch (fb->format->cpp[0]) { in adlp_plane_ctl_arb_slots()
1039 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in skl_plane_ctl_crtc()
1045 if (crtc_state->gamma_enable) in skl_plane_ctl_crtc()
1048 if (crtc_state->csc_enable) in skl_plane_ctl_crtc()
1058 to_i915(plane_state->uapi.plane->dev); in skl_plane_ctl()
1059 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_ctl()
1060 unsigned int rotation = plane_state->hw.rotation; in skl_plane_ctl()
1061 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; in skl_plane_ctl()
1070 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) in skl_plane_ctl()
1073 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) in skl_plane_ctl()
1077 plane_ctl |= skl_plane_ctl_format(fb->format->format); in skl_plane_ctl()
1078 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); in skl_plane_ctl()
1085 if (key->flags & I915_SET_COLORKEY_DESTINATION) in skl_plane_ctl()
1087 else if (key->flags & I915_SET_COLORKEY_SOURCE) in skl_plane_ctl()
1090 /* Wa_22012358565:adl-p */ in skl_plane_ctl()
1099 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in glk_plane_color_ctl_crtc()
1105 if (crtc_state->gamma_enable) in glk_plane_color_ctl_crtc()
1108 if (crtc_state->csc_enable) in glk_plane_color_ctl_crtc()
1118 to_i915(plane_state->uapi.plane->dev); in glk_plane_color_ctl()
1119 const struct drm_framebuffer *fb = plane_state->hw.fb; in glk_plane_color_ctl()
1120 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in glk_plane_color_ctl()
1126 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { in glk_plane_color_ctl()
1127 switch (plane_state->hw.color_encoding) { in glk_plane_color_ctl()
1139 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) in glk_plane_color_ctl()
1141 } else if (fb->format->is_yuv) { in glk_plane_color_ctl()
1143 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) in glk_plane_color_ctl()
1147 if (plane_state->force_black) in glk_plane_color_ctl()
1156 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in skl_surf_address()
1157 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_surf_address()
1158 u32 offset = plane_state->view.color_plane[color_plane].offset; in skl_surf_address() local
1162 * The DPT object contains only one vma, so the VMA's offset in skl_surf_address()
1165 drm_WARN_ON(&i915->drm, plane_state->dpt_vma && in skl_surf_address()
1166 intel_dpt_offset(plane_state->dpt_vma)); in skl_surf_address()
1167 drm_WARN_ON(&i915->drm, offset & 0x1fffff); in skl_surf_address()
1168 return offset >> 9; in skl_surf_address()
1170 drm_WARN_ON(&i915->drm, offset & 0xfff); in skl_surf_address()
1171 return offset; in skl_surf_address()
1183 if (plane_state->decrypt) in skl_plane_surf()
1192 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in skl_plane_aux_dist()
1193 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_aux_dist()
1200 aux_dist = skl_surf_address(plane_state, aux_plane) - in skl_plane_aux_dist()
1211 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; in skl_plane_keyval()
1213 return key->min_value; in skl_plane_keyval()
1218 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; in skl_plane_keymax()
1219 u8 alpha = plane_state->hw.alpha >> 8; in skl_plane_keymax()
1221 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); in skl_plane_keymax()
1226 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; in skl_plane_keymsk()
1227 u8 alpha = plane_state->hw.alpha >> 8; in skl_plane_keymsk()
1230 keymsk = key->channel_mask & 0x7ffffff; in skl_plane_keymsk()
1239 struct drm_i915_private *i915 = to_i915(plane->base.dev); in icl_plane_csc_load_black()
1240 enum plane_id plane_id = plane->id; in icl_plane_csc_load_black()
1241 enum pipe pipe = plane->pipe; in icl_plane_csc_load_black()
1264 if (plane_state->planar_linked_plane && !plane_state->planar_slave) in icl_plane_color_plane()
1275 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_plane_update_noarm()
1276 enum plane_id plane_id = plane->id; in skl_plane_update_noarm()
1277 enum pipe pipe = plane->pipe; in skl_plane_update_noarm()
1279 int crtc_x = plane_state->uapi.dst.x1; in skl_plane_update_noarm()
1280 int crtc_y = plane_state->uapi.dst.y1; in skl_plane_update_noarm()
1281 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in skl_plane_update_noarm()
1282 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; in skl_plane_update_noarm()
1285 if (plane_state->scaler_id >= 0) { in skl_plane_update_noarm()
1295 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); in skl_plane_update_noarm()
1305 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_plane_update_arm()
1306 enum plane_id plane_id = plane->id; in skl_plane_update_arm()
1307 enum pipe pipe = plane->pipe; in skl_plane_update_arm()
1308 u32 x = plane_state->view.color_plane[0].x; in skl_plane_update_arm()
1309 u32 y = plane_state->view.color_plane[0].y; in skl_plane_update_arm() local
1312 plane_ctl = plane_state->ctl | in skl_plane_update_arm()
1316 if (plane->need_async_flip_toggle_wa && in skl_plane_update_arm()
1317 crtc_state->async_flip_planes & BIT(plane->id)) in skl_plane_update_arm()
1321 plane_color_ctl = plane_state->color_ctl | in skl_plane_update_arm()
1329 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); in skl_plane_update_arm()
1335 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | in skl_plane_update_arm()
1336 PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); in skl_plane_update_arm()
1348 if (plane_state->scaler_id >= 0) in skl_plane_update_arm()
1352 * The control register self-arms if the plane was previously in skl_plane_update_arm()
1366 struct drm_i915_private *i915 = to_i915(plane->base.dev); in icl_plane_update_sel_fetch_noarm()
1367 enum pipe pipe = plane->pipe; in icl_plane_update_sel_fetch_noarm()
1370 int x, y; in icl_plane_update_sel_fetch_noarm() local
1372 if (!crtc_state->enable_psr2_sel_fetch) in icl_plane_update_sel_fetch_noarm()
1375 clip = &plane_state->psr2_sel_fetch_area; in icl_plane_update_sel_fetch_noarm()
1377 if (crtc_state->enable_psr2_su_region_et) in icl_plane_update_sel_fetch_noarm()
1378 y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1); in icl_plane_update_sel_fetch_noarm()
1380 y = (clip->y1 + plane_state->uapi.dst.y1); in icl_plane_update_sel_fetch_noarm()
1381 val = y << 16; in icl_plane_update_sel_fetch_noarm()
1382 val |= plane_state->uapi.dst.x1; in icl_plane_update_sel_fetch_noarm()
1383 intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); in icl_plane_update_sel_fetch_noarm()
1385 x = plane_state->view.color_plane[color_plane].x; in icl_plane_update_sel_fetch_noarm()
1388 * From Bspec: UV surface Start Y Position = half of Y plane Y in icl_plane_update_sel_fetch_noarm()
1392 y = plane_state->view.color_plane[color_plane].y + clip->y1; in icl_plane_update_sel_fetch_noarm()
1394 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; in icl_plane_update_sel_fetch_noarm()
1396 val = y << 16 | x; in icl_plane_update_sel_fetch_noarm()
1398 intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), in icl_plane_update_sel_fetch_noarm()
1402 val = (drm_rect_height(clip) - 1) << 16; in icl_plane_update_sel_fetch_noarm()
1403 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; in icl_plane_update_sel_fetch_noarm()
1404 intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); in icl_plane_update_sel_fetch_noarm()
1412 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in icl_plane_update_noarm()
1413 enum plane_id plane_id = plane->id; in icl_plane_update_noarm()
1414 enum pipe pipe = plane->pipe; in icl_plane_update_noarm()
1417 const struct drm_framebuffer *fb = plane_state->hw.fb; in icl_plane_update_noarm()
1418 int crtc_x = plane_state->uapi.dst.x1; in icl_plane_update_noarm()
1419 int crtc_y = plane_state->uapi.dst.y1; in icl_plane_update_noarm()
1420 int x = plane_state->view.color_plane[color_plane].x; in icl_plane_update_noarm()
1421 int y = plane_state->view.color_plane[color_plane].y; in icl_plane_update_noarm() local
1422 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in icl_plane_update_noarm()
1423 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; in icl_plane_update_noarm()
1426 plane_color_ctl = plane_state->color_ctl | in icl_plane_update_noarm()
1430 if (plane_state->scaler_id >= 0) { in icl_plane_update_noarm()
1440 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); in icl_plane_update_noarm()
1447 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); in icl_plane_update_noarm()
1449 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { in icl_plane_update_noarm()
1451 lower_32_bits(plane_state->ccval)); in icl_plane_update_noarm()
1453 upper_32_bits(plane_state->ccval)); in icl_plane_update_noarm()
1463 plane_state->cus_ctl); in icl_plane_update_noarm()
1467 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) in icl_plane_update_noarm()
1476 if (plane_state->force_black) in icl_plane_update_noarm()
1486 struct drm_i915_private *i915 = to_i915(plane->base.dev); in icl_plane_update_sel_fetch_arm()
1487 enum pipe pipe = plane->pipe; in icl_plane_update_sel_fetch_arm()
1489 if (!crtc_state->enable_psr2_sel_fetch) in icl_plane_update_sel_fetch_arm()
1492 if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) in icl_plane_update_sel_fetch_arm()
1493 intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), in icl_plane_update_sel_fetch_arm()
1504 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in icl_plane_update_arm()
1505 enum plane_id plane_id = plane->id; in icl_plane_update_arm()
1506 enum pipe pipe = plane->pipe; in icl_plane_update_arm()
1510 plane_ctl = plane_state->ctl | in icl_plane_update_arm()
1520 if (plane_state->scaler_id >= 0) in icl_plane_update_arm()
1526 * The control register self-arms if the plane was previously in icl_plane_update_arm()
1541 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_plane_async_flip()
1542 enum plane_id plane_id = plane->id; in skl_plane_async_flip()
1543 enum pipe pipe = plane->pipe; in skl_plane_async_flip()
1544 u32 plane_ctl = plane_state->ctl; in skl_plane_async_flip()
1571 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in skl_plane_check_fb()
1572 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_plane_check_fb()
1573 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_check_fb()
1574 unsigned int rotation = plane_state->hw.rotation; in skl_plane_check_fb()
1580 intel_fb_is_ccs_modifier(fb->modifier)) { in skl_plane_check_fb()
1581 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_fb()
1584 return -EINVAL; in skl_plane_check_fb()
1588 fb->modifier == DRM_FORMAT_MOD_LINEAR) { in skl_plane_check_fb()
1589 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_fb()
1591 return -EINVAL; in skl_plane_check_fb()
1598 intel_fb_is_tile4_modifier(fb->modifier) && in skl_plane_check_fb()
1600 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_fb()
1602 return -EINVAL; in skl_plane_check_fb()
1607 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_fb()
1608 "Y/Yf tiling required for 90/270!\n"); in skl_plane_check_fb()
1609 return -EINVAL; in skl_plane_check_fb()
1614 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. in skl_plane_check_fb()
1616 switch (fb->format->format) { in skl_plane_check_fb()
1631 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_fb()
1633 &fb->format->format); in skl_plane_check_fb()
1634 return -EINVAL; in skl_plane_check_fb()
1640 /* Y-tiling is not supported in IF-ID Interlace mode */ in skl_plane_check_fb()
1641 if (crtc_state->hw.enable && in skl_plane_check_fb()
1642 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && in skl_plane_check_fb()
1643 fb->modifier != DRM_FORMAT_MOD_LINEAR && in skl_plane_check_fb()
1644 fb->modifier != I915_FORMAT_MOD_X_TILED) { in skl_plane_check_fb()
1645 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_fb()
1646 "Y/Yf tiling not supported in IF-ID mode\n"); in skl_plane_check_fb()
1647 return -EINVAL; in skl_plane_check_fb()
1650 /* Wa_1606054188:tgl,adl-s */ in skl_plane_check_fb()
1652 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && in skl_plane_check_fb()
1653 intel_format_is_p01x(fb->format->format)) { in skl_plane_check_fb()
1654 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_fb()
1656 return -EINVAL; in skl_plane_check_fb()
1666 to_i915(plane_state->uapi.plane->dev); in skl_plane_check_dst_coordinates()
1667 int crtc_x = plane_state->uapi.dst.x1; in skl_plane_check_dst_coordinates()
1668 int crtc_w = drm_rect_width(&plane_state->uapi.dst); in skl_plane_check_dst_coordinates()
1669 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); in skl_plane_check_dst_coordinates()
1681 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { in skl_plane_check_dst_coordinates()
1682 drm_dbg_kms(&dev_priv->drm, in skl_plane_check_dst_coordinates()
1683 "requested plane X %s position %d invalid (valid range %d-%d)\n", in skl_plane_check_dst_coordinates()
1686 4, pipe_src_w - 4); in skl_plane_check_dst_coordinates()
1687 return -ERANGE; in skl_plane_check_dst_coordinates()
1695 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in skl_plane_check_nv12_rotation()
1696 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_check_nv12_rotation()
1697 unsigned int rotation = plane_state->hw.rotation; in skl_plane_check_nv12_rotation()
1698 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in skl_plane_check_nv12_rotation()
1701 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && in skl_plane_check_nv12_rotation()
1705 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); in skl_plane_check_nv12_rotation()
1706 return -EINVAL; in skl_plane_check_nv12_rotation()
1722 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) in skl_plane_max_scale()
1723 return 0x30000 - 1; in skl_plane_max_scale()
1725 return 0x20000 - 1; in skl_plane_max_scale()
1733 if (plane->min_width) in intel_plane_min_width()
1734 return plane->min_width(fb, color_plane, rotation); in intel_plane_min_width()
1744 if (plane->max_width) in intel_plane_max_width()
1745 return plane->max_width(fb, color_plane, rotation); in intel_plane_max_width()
1755 if (plane->max_height) in intel_plane_max_height()
1756 return plane->max_height(fb, color_plane, rotation); in intel_plane_max_height()
1766 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in skl_check_main_ccs_coordinates()
1767 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_main_ccs_coordinates()
1768 int aux_x = plane_state->view.color_plane[ccs_plane].x; in skl_check_main_ccs_coordinates()
1769 int aux_y = plane_state->view.color_plane[ccs_plane].y; in skl_check_main_ccs_coordinates()
1770 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; in skl_check_main_ccs_coordinates()
1771 unsigned int alignment = plane->min_alignment(plane, fb, ccs_plane); in skl_check_main_ccs_coordinates()
1777 int x, y; in skl_check_main_ccs_coordinates() local
1786 y = aux_y / vsub; in skl_check_main_ccs_coordinates()
1787 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, in skl_check_main_ccs_coordinates()
1791 aux_offset - alignment); in skl_check_main_ccs_coordinates()
1793 aux_y = y * vsub + aux_y % vsub; in skl_check_main_ccs_coordinates()
1799 plane_state->view.color_plane[ccs_plane].offset = aux_offset; in skl_check_main_ccs_coordinates()
1800 plane_state->view.color_plane[ccs_plane].x = aux_x; in skl_check_main_ccs_coordinates()
1801 plane_state->view.color_plane[ccs_plane].y = aux_y; in skl_check_main_ccs_coordinates()
1808 int *x, int *y, u32 *offset) in skl_calc_main_surface_offset() argument
1810 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in skl_calc_main_surface_offset()
1811 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_calc_main_surface_offset()
1812 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_calc_main_surface_offset()
1814 u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; in skl_calc_main_surface_offset()
1815 unsigned int alignment = plane->min_alignment(plane, fb, 0); in skl_calc_main_surface_offset()
1816 int w = drm_rect_width(&plane_state->uapi.src) >> 16; in skl_calc_main_surface_offset()
1818 intel_add_fb_offsets(x, y, plane_state, 0); in skl_calc_main_surface_offset()
1819 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); in skl_calc_main_surface_offset()
1820 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) in skl_calc_main_surface_offset()
1821 return -EINVAL; in skl_calc_main_surface_offset()
1824 * AUX surface offset is specified as the distance from the in skl_calc_main_surface_offset()
1825 * main surface offset, and it must be non-negative. Make in skl_calc_main_surface_offset()
1828 if (aux_plane && *offset > aux_offset) in skl_calc_main_surface_offset()
1829 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, in skl_calc_main_surface_offset()
1830 *offset, in skl_calc_main_surface_offset()
1831 aux_offset & ~(alignment - 1)); in skl_calc_main_surface_offset()
1834 * When using an X-tiled surface, the plane blows up in skl_calc_main_surface_offset()
1835 * if the x offset + width exceed the stride. in skl_calc_main_surface_offset()
1837 * TODO: linear and Y-tiled seem fine, Yf untested, in skl_calc_main_surface_offset()
1839 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { in skl_calc_main_surface_offset()
1840 int cpp = fb->format->cpp[0]; in skl_calc_main_surface_offset()
1842 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { in skl_calc_main_surface_offset()
1843 if (*offset == 0) { in skl_calc_main_surface_offset()
1844 drm_dbg_kms(&dev_priv->drm, in skl_calc_main_surface_offset()
1845 "Unable to find suitable display surface offset due to X-tiling\n"); in skl_calc_main_surface_offset()
1846 return -EINVAL; in skl_calc_main_surface_offset()
1849 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, in skl_calc_main_surface_offset()
1850 *offset, in skl_calc_main_surface_offset()
1851 *offset - alignment); in skl_calc_main_surface_offset()
1860 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in skl_check_main_surface()
1861 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_check_main_surface()
1862 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_main_surface()
1863 unsigned int rotation = plane_state->hw.rotation; in skl_check_main_surface()
1864 int x = plane_state->uapi.src.x1 >> 16; in skl_check_main_surface()
1865 int y = plane_state->uapi.src.y1 >> 16; in skl_check_main_surface() local
1866 int w = drm_rect_width(&plane_state->uapi.src) >> 16; in skl_check_main_surface()
1867 int h = drm_rect_height(&plane_state->uapi.src) >> 16; in skl_check_main_surface()
1871 unsigned int alignment = plane->min_alignment(plane, fb, 0); in skl_check_main_surface()
1873 u32 offset; in skl_check_main_surface() local
1877 drm_dbg_kms(&dev_priv->drm, in skl_check_main_surface()
1878 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", in skl_check_main_surface()
1880 return -EINVAL; in skl_check_main_surface()
1883 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); in skl_check_main_surface()
1888 * CCS AUX surface doesn't have its own x/y offsets, we must make sure in skl_check_main_surface()
1889 * they match with the main surface x/y offsets. On DG2 in skl_check_main_surface()
1892 if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) { in skl_check_main_surface()
1893 while (!skl_check_main_ccs_coordinates(plane_state, x, y, in skl_check_main_surface()
1894 offset, aux_plane)) { in skl_check_main_surface()
1895 if (offset == 0) in skl_check_main_surface()
1898 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, in skl_check_main_surface()
1899 offset, offset - alignment); in skl_check_main_surface()
1902 if (x != plane_state->view.color_plane[aux_plane].x || in skl_check_main_surface()
1903 y != plane_state->view.color_plane[aux_plane].y) { in skl_check_main_surface()
1904 drm_dbg_kms(&dev_priv->drm, in skl_check_main_surface()
1905 "Unable to find suitable display surface offset due to CCS\n"); in skl_check_main_surface()
1906 return -EINVAL; in skl_check_main_surface()
1911 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); in skl_check_main_surface()
1913 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); in skl_check_main_surface()
1915 plane_state->view.color_plane[0].offset = offset; in skl_check_main_surface()
1916 plane_state->view.color_plane[0].x = x; in skl_check_main_surface()
1917 plane_state->view.color_plane[0].y = y; in skl_check_main_surface()
1923 drm_rect_translate_to(&plane_state->uapi.src, in skl_check_main_surface()
1924 x << 16, y << 16); in skl_check_main_surface()
1931 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in skl_check_nv12_aux_surface()
1932 struct drm_i915_private *i915 = to_i915(plane->base.dev); in skl_check_nv12_aux_surface()
1933 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_nv12_aux_surface()
1934 unsigned int rotation = plane_state->hw.rotation; in skl_check_nv12_aux_surface()
1936 int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ? in skl_check_nv12_aux_surface()
1940 int x = plane_state->uapi.src.x1 >> 17; in skl_check_nv12_aux_surface()
1941 int y = plane_state->uapi.src.y1 >> 17; in skl_check_nv12_aux_surface() local
1942 int w = drm_rect_width(&plane_state->uapi.src) >> 17; in skl_check_nv12_aux_surface()
1943 int h = drm_rect_height(&plane_state->uapi.src) >> 17; in skl_check_nv12_aux_surface()
1944 u32 offset; in skl_check_nv12_aux_surface() local
1948 drm_dbg_kms(&i915->drm, in skl_check_nv12_aux_surface()
1951 return -EINVAL; in skl_check_nv12_aux_surface()
1954 intel_add_fb_offsets(&x, &y, plane_state, uv_plane); in skl_check_nv12_aux_surface()
1955 offset = intel_plane_compute_aligned_offset(&x, &y, in skl_check_nv12_aux_surface()
1959 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; in skl_check_nv12_aux_surface()
1960 unsigned int alignment = plane->min_alignment(plane, fb, uv_plane); in skl_check_nv12_aux_surface()
1962 if (offset > aux_offset) in skl_check_nv12_aux_surface()
1963 offset = intel_plane_adjust_aligned_offset(&x, &y, in skl_check_nv12_aux_surface()
1966 offset, in skl_check_nv12_aux_surface()
1967 aux_offset & ~(alignment - 1)); in skl_check_nv12_aux_surface()
1969 while (!skl_check_main_ccs_coordinates(plane_state, x, y, in skl_check_nv12_aux_surface()
1970 offset, ccs_plane)) { in skl_check_nv12_aux_surface()
1971 if (offset == 0) in skl_check_nv12_aux_surface()
1974 offset = intel_plane_adjust_aligned_offset(&x, &y, in skl_check_nv12_aux_surface()
1977 offset, offset - alignment); in skl_check_nv12_aux_surface()
1980 if (x != plane_state->view.color_plane[ccs_plane].x || in skl_check_nv12_aux_surface()
1981 y != plane_state->view.color_plane[ccs_plane].y) { in skl_check_nv12_aux_surface()
1982 drm_dbg_kms(&i915->drm, in skl_check_nv12_aux_surface()
1983 "Unable to find suitable display surface offset due to CCS\n"); in skl_check_nv12_aux_surface()
1984 return -EINVAL; in skl_check_nv12_aux_surface()
1989 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); in skl_check_nv12_aux_surface()
1991 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); in skl_check_nv12_aux_surface()
1993 plane_state->view.color_plane[uv_plane].offset = offset; in skl_check_nv12_aux_surface()
1994 plane_state->view.color_plane[uv_plane].x = x; in skl_check_nv12_aux_surface()
1995 plane_state->view.color_plane[uv_plane].y = y; in skl_check_nv12_aux_surface()
2002 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_ccs_aux_surface()
2003 int src_x = plane_state->uapi.src.x1 >> 16; in skl_check_ccs_aux_surface()
2004 int src_y = plane_state->uapi.src.y1 >> 16; in skl_check_ccs_aux_surface()
2005 u32 offset; in skl_check_ccs_aux_surface() local
2008 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { in skl_check_ccs_aux_surface()
2011 int x, y; in skl_check_ccs_aux_surface() local
2023 y = src_y / vsub; in skl_check_ccs_aux_surface()
2025 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); in skl_check_ccs_aux_surface()
2027 offset = intel_plane_compute_aligned_offset(&x, &y, in skl_check_ccs_aux_surface()
2031 plane_state->view.color_plane[ccs_plane].offset = offset; in skl_check_ccs_aux_surface()
2032 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub; in skl_check_ccs_aux_surface()
2033 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub; in skl_check_ccs_aux_surface()
2041 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_check_plane_surface()
2048 if (!plane_state->uapi.visible) in skl_check_plane_surface()
2055 if (intel_fb_is_ccs_modifier(fb->modifier)) { in skl_check_plane_surface()
2061 if (intel_format_info_is_yuv_semiplanar(fb->format, in skl_check_plane_surface()
2062 fb->modifier)) { in skl_check_plane_surface()
2080 switch (fb->format->format) { in skl_fb_scalable()
2087 return DISPLAY_VER(to_i915(fb->dev)) >= 11; in skl_fb_scalable()
2095 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in check_protection()
2096 struct drm_i915_private *i915 = to_i915(plane->base.dev); in check_protection()
2097 const struct drm_framebuffer *fb = plane_state->hw.fb; in check_protection()
2103 plane_state->decrypt = intel_pxp_key_check(i915->pxp, obj, false) == 0; in check_protection()
2104 plane_state->force_black = i915_gem_object_is_protected(obj) && in check_protection()
2105 !plane_state->decrypt; in check_protection()
2111 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in skl_plane_check()
2112 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in skl_plane_check()
2113 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_check()
2123 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { in skl_plane_check()
2137 if (!plane_state->uapi.visible) in skl_plane_check()
2155 if (!(plane_state->hw.alpha >> 8)) in skl_plane_check()
2156 plane_state->uapi.visible = false; in skl_plane_check()
2158 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); in skl_plane_check()
2161 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, in skl_plane_check()
2164 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && in skl_plane_check()
2165 icl_is_hdr_plane(dev_priv, plane->id)) in skl_plane_check()
2166 /* Enable and use MPEG-2 chroma siting */ in skl_plane_check()
2167 plane_state->cus_ctl = PLANE_CUS_ENABLE | in skl_plane_check()
2171 plane_state->cus_ctl = 0; in skl_plane_check()
2178 return pipe - PIPE_A + INTEL_FBC_A; in skl_fbc_id_for_pipe()
2184 if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) in skl_plane_has_fbc()
2199 return dev_priv->display.fbc[fbc_id]; in skl_plane_fbc()
2389 struct drm_i915_private *i915 = to_i915(plane->base.dev); in skl_plane_enable_flip_done()
2390 enum pipe pipe = plane->pipe; in skl_plane_enable_flip_done()
2392 spin_lock_irq(&i915->irq_lock); in skl_plane_enable_flip_done()
2393 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); in skl_plane_enable_flip_done()
2394 spin_unlock_irq(&i915->irq_lock); in skl_plane_enable_flip_done()
2400 struct drm_i915_private *i915 = to_i915(plane->base.dev); in skl_plane_disable_flip_done()
2401 enum pipe pipe = plane->pipe; in skl_plane_disable_flip_done()
2403 spin_lock_irq(&i915->irq_lock); in skl_plane_disable_flip_done()
2404 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); in skl_plane_disable_flip_done()
2405 spin_unlock_irq(&i915->irq_lock); in skl_plane_disable_flip_done()
2491 plane->pipe = pipe; in skl_universal_plane_create()
2492 plane->id = plane_id; in skl_universal_plane_create()
2493 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); in skl_universal_plane_create()
2498 plane->min_width = icl_plane_min_width; in skl_universal_plane_create()
2500 plane->max_width = icl_hdr_plane_max_width; in skl_universal_plane_create()
2502 plane->max_width = icl_sdr_plane_max_width; in skl_universal_plane_create()
2503 plane->max_height = icl_plane_max_height; in skl_universal_plane_create()
2504 plane->min_cdclk = icl_plane_min_cdclk; in skl_universal_plane_create()
2506 plane->max_width = glk_plane_max_width; in skl_universal_plane_create()
2507 plane->max_height = skl_plane_max_height; in skl_universal_plane_create()
2508 plane->min_cdclk = glk_plane_min_cdclk; in skl_universal_plane_create()
2510 plane->max_width = skl_plane_max_width; in skl_universal_plane_create()
2511 plane->max_height = skl_plane_max_height; in skl_universal_plane_create()
2512 plane->min_cdclk = skl_plane_min_cdclk; in skl_universal_plane_create()
2516 plane->max_stride = adl_plane_max_stride; in skl_universal_plane_create()
2518 plane->max_stride = skl_plane_max_stride; in skl_universal_plane_create()
2521 plane->min_alignment = tgl_plane_min_alignment; in skl_universal_plane_create()
2523 plane->min_alignment = skl_plane_min_alignment; in skl_universal_plane_create()
2526 plane->update_noarm = icl_plane_update_noarm; in skl_universal_plane_create()
2527 plane->update_arm = icl_plane_update_arm; in skl_universal_plane_create()
2528 plane->disable_arm = icl_plane_disable_arm; in skl_universal_plane_create()
2530 plane->update_noarm = skl_plane_update_noarm; in skl_universal_plane_create()
2531 plane->update_arm = skl_plane_update_arm; in skl_universal_plane_create()
2532 plane->disable_arm = skl_plane_disable_arm; in skl_universal_plane_create()
2534 plane->get_hw_state = skl_plane_get_hw_state; in skl_universal_plane_create()
2535 plane->check_plane = skl_plane_check; in skl_universal_plane_create()
2538 plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); in skl_universal_plane_create()
2539 plane->async_flip = skl_plane_async_flip; in skl_universal_plane_create()
2540 plane->enable_flip_done = skl_plane_enable_flip_done; in skl_universal_plane_create()
2541 plane->disable_flip_done = skl_plane_disable_flip_done; in skl_universal_plane_create()
2567 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, in skl_universal_plane_create()
2589 drm_plane_create_rotation_property(&plane->base, in skl_universal_plane_create()
2598 drm_plane_create_color_properties(&plane->base, in skl_universal_plane_create()
2605 drm_plane_create_alpha_property(&plane->base); in skl_universal_plane_create()
2606 drm_plane_create_blend_mode_property(&plane->base, in skl_universal_plane_create()
2611 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); in skl_universal_plane_create()
2614 drm_plane_enable_fb_damage_clips(&plane->base); in skl_universal_plane_create()
2617 drm_plane_create_scaling_filter_property(&plane->base, in skl_universal_plane_create()
2635 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); in skl_get_initial_plane_config()
2636 struct drm_device *dev = crtc->base.dev; in skl_get_initial_plane_config()
2638 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in skl_get_initial_plane_config()
2639 enum plane_id plane_id = plane->id; in skl_get_initial_plane_config()
2641 u32 val, base, offset, stride_mult, tiling, alpha; in skl_get_initial_plane_config() local
2648 if (!plane->get_hw_state(plane, &pipe)) in skl_get_initial_plane_config()
2651 drm_WARN_ON(dev, pipe != crtc->pipe); in skl_get_initial_plane_config()
2653 if (crtc_state->joiner_pipes) { in skl_get_initial_plane_config()
2654 drm_dbg_kms(&dev_priv->drm, in skl_get_initial_plane_config()
2661 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); in skl_get_initial_plane_config()
2665 fb = &intel_fb->base; in skl_get_initial_plane_config()
2667 fb->dev = dev; in skl_get_initial_plane_config()
2687 fb->format = drm_format_info(fourcc); in skl_get_initial_plane_config()
2692 fb->modifier = DRM_FORMAT_MOD_LINEAR; in skl_get_initial_plane_config()
2695 plane_config->tiling = I915_TILING_X; in skl_get_initial_plane_config()
2696 fb->modifier = I915_FORMAT_MOD_X_TILED; in skl_get_initial_plane_config()
2699 plane_config->tiling = I915_TILING_Y; in skl_get_initial_plane_config()
2702 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS; in skl_get_initial_plane_config()
2704 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; in skl_get_initial_plane_config()
2706 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; in skl_get_initial_plane_config()
2709 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS; in skl_get_initial_plane_config()
2711 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; in skl_get_initial_plane_config()
2713 fb->modifier = I915_FORMAT_MOD_Y_TILED; in skl_get_initial_plane_config()
2721 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS; in skl_get_initial_plane_config()
2723 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; in skl_get_initial_plane_config()
2725 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; in skl_get_initial_plane_config()
2727 fb->modifier = I915_FORMAT_MOD_4_TILED; in skl_get_initial_plane_config()
2730 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; in skl_get_initial_plane_config()
2732 fb->modifier = I915_FORMAT_MOD_Yf_TILED; in skl_get_initial_plane_config()
2740 if (!dev_priv->display.params.enable_dpt && in skl_get_initial_plane_config()
2741 intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { in skl_get_initial_plane_config()
2742 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); in skl_get_initial_plane_config()
2752 plane_config->rotation = DRM_MODE_ROTATE_0; in skl_get_initial_plane_config()
2755 plane_config->rotation = DRM_MODE_ROTATE_270; in skl_get_initial_plane_config()
2758 plane_config->rotation = DRM_MODE_ROTATE_180; in skl_get_initial_plane_config()
2761 plane_config->rotation = DRM_MODE_ROTATE_90; in skl_get_initial_plane_config()
2766 plane_config->rotation |= DRM_MODE_REFLECT_X; in skl_get_initial_plane_config()
2769 if (drm_rotation_90_or_270(plane_config->rotation)) in skl_get_initial_plane_config()
2773 plane_config->base = base; in skl_get_initial_plane_config()
2775 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); in skl_get_initial_plane_config()
2776 drm_WARN_ON(&dev_priv->drm, offset != 0); in skl_get_initial_plane_config()
2779 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; in skl_get_initial_plane_config()
2780 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; in skl_get_initial_plane_config()
2785 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; in skl_get_initial_plane_config()
2787 aligned_height = intel_fb_align_height(fb, 0, fb->height); in skl_get_initial_plane_config()
2789 plane_config->size = fb->pitches[0] * aligned_height; in skl_get_initial_plane_config()
2791 drm_dbg_kms(&dev_priv->drm, in skl_get_initial_plane_config()
2792 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", in skl_get_initial_plane_config()
2793 crtc->base.name, plane->base.name, fb->width, fb->height, in skl_get_initial_plane_config()
2794 fb->format->cpp[0] * 8, base, fb->pitches[0], in skl_get_initial_plane_config()
2795 plane_config->size); in skl_get_initial_plane_config()
2797 plane_config->fb = intel_fb; in skl_get_initial_plane_config()
2807 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_fixup_initial_plane_config()
2808 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in skl_fixup_initial_plane_config()
2810 to_intel_plane_state(plane->base.state); in skl_fixup_initial_plane_config()
2811 enum plane_id plane_id = plane->id; in skl_fixup_initial_plane_config()
2812 enum pipe pipe = crtc->pipe; in skl_fixup_initial_plane_config()
2815 if (!plane_state->uapi.visible) in skl_fixup_initial_plane_config()
2824 if (plane_config->base == base) in skl_fixup_initial_plane_config()