408 				int pps, u32 pps_val)  in intel_dsc_pps_write()  argument
423 		intel_de_write(i915, dsc_reg[i], pps_val);  in intel_dsc_pps_write()
433 	u32 pps_val;  in intel_dsc_pps_configure()  local
441 	pps_val = DSC_PPS0_VER_MAJOR(1) |  in intel_dsc_pps_configure()
446 		pps_val |= DSC_PPS0_ALT_ICH_SEL;  in intel_dsc_pps_configure()
448 			pps_val |= DSC_PPS0_NATIVE_420_ENABLE;  in intel_dsc_pps_configure()
450 			pps_val |= DSC_PPS0_NATIVE_422_ENABLE;  in intel_dsc_pps_configure()
453 		pps_val |= DSC_PPS0_BLOCK_PREDICTION;  in intel_dsc_pps_configure()
455 		pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;  in intel_dsc_pps_configure()
457 		pps_val |= DSC_PPS0_422_ENABLE;  in intel_dsc_pps_configure()
459 		pps_val |= DSC_PPS0_VBR_ENABLE;  in intel_dsc_pps_configure()
460 	intel_dsc_pps_write(crtc_state, 0, pps_val);  in intel_dsc_pps_configure()
463 	pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);  in intel_dsc_pps_configure()
464 	intel_dsc_pps_write(crtc_state, 1, pps_val);  in intel_dsc_pps_configure()
467 	pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |  in intel_dsc_pps_configure()
469 	intel_dsc_pps_write(crtc_state, 2, pps_val);  in intel_dsc_pps_configure()
472 	pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |  in intel_dsc_pps_configure()
474 	intel_dsc_pps_write(crtc_state, 3, pps_val);  in intel_dsc_pps_configure()
477 	pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |  in intel_dsc_pps_configure()
479 	intel_dsc_pps_write(crtc_state, 4, pps_val);  in intel_dsc_pps_configure()
482 	pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |  in intel_dsc_pps_configure()
484 	intel_dsc_pps_write(crtc_state, 5, pps_val);  in intel_dsc_pps_configure()
487 	pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |  in intel_dsc_pps_configure()
491 	intel_dsc_pps_write(crtc_state, 6, pps_val);  in intel_dsc_pps_configure()
494 	pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |  in intel_dsc_pps_configure()
496 	intel_dsc_pps_write(crtc_state, 7, pps_val);  in intel_dsc_pps_configure()
499 	pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |  in intel_dsc_pps_configure()
501 	intel_dsc_pps_write(crtc_state, 8, pps_val);  in intel_dsc_pps_configure()
504 	pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |  in intel_dsc_pps_configure()
506 	intel_dsc_pps_write(crtc_state, 9, pps_val);  in intel_dsc_pps_configure()
509 	pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |  in intel_dsc_pps_configure()
513 	intel_dsc_pps_write(crtc_state, 10, pps_val);  in intel_dsc_pps_configure()
516 	pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |  in intel_dsc_pps_configure()
521 	intel_dsc_pps_write(crtc_state, 16, pps_val);  in intel_dsc_pps_configure()
525 		pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);  in intel_dsc_pps_configure()
526 		intel_dsc_pps_write(crtc_state, 17, pps_val);  in intel_dsc_pps_configure()
529 		pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |  in intel_dsc_pps_configure()
531 		intel_dsc_pps_write(crtc_state, 18, pps_val);  in intel_dsc_pps_configure()