Lines Matching +full:0 +full:x000003ff
12 #define TV_CTL _MMIO(0x68000)
20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
31 # define TV_OVERSAMPLE_4X (0 << 18)
54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
57 # define TV_FUSE_STATE_ENABLED (0 << 4)
63 # define TV_TEST_MODE_NORMAL (0 << 0)
65 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
67 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
69 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
71 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
73 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
79 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
80 # define TV_TEST_MODE_MASK (7 << 0)
82 #define TV_DAC _MMIO(0x68004)
83 # define TV_DAC_SAVE 0x00ffff00
114 # define DAC_A_1_3_V (0 << 4)
118 # define DAC_B_1_3_V (0 << 2)
122 # define DAC_C_1_3_V (0 << 0)
123 # define DAC_C_1_1_V (1 << 0)
124 # define DAC_C_0_7_V (2 << 0)
125 # define DAC_C_MASK (3 << 0)
131 * -1 (0x3) being the only legal negative value.
133 #define TV_CSC_Y _MMIO(0x68010)
134 # define TV_RY_MASK 0x07ff0000
136 # define TV_GY_MASK 0x00000fff
137 # define TV_GY_SHIFT 0
139 #define TV_CSC_Y2 _MMIO(0x68014)
140 # define TV_BY_MASK 0x07ff0000
147 # define TV_AY_MASK 0x000003ff
148 # define TV_AY_SHIFT 0
150 #define TV_CSC_U _MMIO(0x68018)
151 # define TV_RU_MASK 0x07ff0000
153 # define TV_GU_MASK 0x000007ff
154 # define TV_GU_SHIFT 0
156 #define TV_CSC_U2 _MMIO(0x6801c)
157 # define TV_BU_MASK 0x07ff0000
164 # define TV_AU_MASK 0x000003ff
165 # define TV_AU_SHIFT 0
167 #define TV_CSC_V _MMIO(0x68020)
168 # define TV_RV_MASK 0x0fff0000
170 # define TV_GV_MASK 0x000007ff
171 # define TV_GV_SHIFT 0
173 #define TV_CSC_V2 _MMIO(0x68024)
174 # define TV_BV_MASK 0x07ff0000
181 # define TV_AV_MASK 0x000007ff
182 # define TV_AV_SHIFT 0
184 #define TV_CLR_KNOBS _MMIO(0x68028)
186 # define TV_BRIGHTNESS_MASK 0xff000000
189 # define TV_CONTRAST_MASK 0x00ff0000
192 # define TV_SATURATION_MASK 0x0000ff00
195 # define TV_HUE_MASK 0x000000ff
196 # define TV_HUE_SHIFT 0
198 #define TV_CLR_LEVEL _MMIO(0x6802c)
200 # define TV_BLACK_LEVEL_MASK 0x01ff0000
203 # define TV_BLANK_LEVEL_MASK 0x000001ff
204 # define TV_BLANK_LEVEL_SHIFT 0
206 #define TV_H_CTL_1 _MMIO(0x68030)
208 # define TV_HSYNC_END_MASK 0x1fff0000
211 # define TV_HTOTAL_MASK 0x00001fff
212 # define TV_HTOTAL_SHIFT 0
214 #define TV_H_CTL_2 _MMIO(0x68034)
219 # define TV_HBURST_START_MASK 0x1fff0000
221 # define TV_HBURST_LEN_SHIFT 0
222 # define TV_HBURST_LEN_MASK 0x0001fff
224 #define TV_H_CTL_3 _MMIO(0x68038)
227 # define TV_HBLANK_END_MASK 0x1fff0000
229 # define TV_HBLANK_START_SHIFT 0
230 # define TV_HBLANK_START_MASK 0x0001fff
232 #define TV_V_CTL_1 _MMIO(0x6803c)
235 # define TV_NBR_END_MASK 0x07ff0000
238 # define TV_VI_END_F1_MASK 0x00003f00
240 # define TV_VI_END_F2_SHIFT 0
241 # define TV_VI_END_F2_MASK 0x0000003f
243 #define TV_V_CTL_2 _MMIO(0x68040)
245 # define TV_VSYNC_LEN_MASK 0x07ff0000
250 # define TV_VSYNC_START_F1_MASK 0x00007f00
256 # define TV_VSYNC_START_F2_MASK 0x0000007f
257 # define TV_VSYNC_START_F2_SHIFT 0
259 #define TV_V_CTL_3 _MMIO(0x68044)
263 # define TV_VEQ_LEN_MASK 0x007f0000
268 # define TV_VEQ_START_F1_MASK 0x0007f00
274 # define TV_VEQ_START_F2_MASK 0x000007f
275 # define TV_VEQ_START_F2_SHIFT 0
277 #define TV_V_CTL_4 _MMIO(0x68048)
282 # define TV_VBURST_START_F1_MASK 0x003f0000
288 # define TV_VBURST_END_F1_MASK 0x000000ff
289 # define TV_VBURST_END_F1_SHIFT 0
291 #define TV_V_CTL_5 _MMIO(0x6804c)
296 # define TV_VBURST_START_F2_MASK 0x003f0000
302 # define TV_VBURST_END_F2_MASK 0x000000ff
303 # define TV_VBURST_END_F2_SHIFT 0
305 #define TV_V_CTL_6 _MMIO(0x68050)
310 # define TV_VBURST_START_F3_MASK 0x003f0000
316 # define TV_VBURST_END_F3_MASK 0x000000ff
317 # define TV_VBURST_END_F3_SHIFT 0
319 #define TV_V_CTL_7 _MMIO(0x68054)
324 # define TV_VBURST_START_F4_MASK 0x003f0000
330 # define TV_VBURST_END_F4_MASK 0x000000ff
331 # define TV_VBURST_END_F4_SHIFT 0
333 #define TV_SC_CTL_1 _MMIO(0x68060)
341 # define TV_SC_RESET_EVERY_2 (0 << 24)
349 # define TV_BURST_LEVEL_MASK 0x00ff0000
352 # define TV_SCDDA1_INC_MASK 0x00000fff
353 # define TV_SCDDA1_INC_SHIFT 0
355 #define TV_SC_CTL_2 _MMIO(0x68064)
357 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
360 # define TV_SCDDA2_INC_MASK 0x00007fff
361 # define TV_SCDDA2_INC_SHIFT 0
363 #define TV_SC_CTL_3 _MMIO(0x68068)
365 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
368 # define TV_SCDDA3_INC_MASK 0x00007fff
369 # define TV_SCDDA3_INC_SHIFT 0
371 #define TV_WIN_POS _MMIO(0x68070)
373 # define TV_XPOS_MASK 0x1fff0000
376 # define TV_YPOS_MASK 0x00000fff
377 # define TV_YPOS_SHIFT 0
379 #define TV_WIN_SIZE _MMIO(0x68074)
381 # define TV_XSIZE_MASK 0x1fff0000
388 # define TV_YSIZE_MASK 0x00000fff
389 # define TV_YSIZE_SHIFT 0
391 #define TV_FILTER_CTL_1 _MMIO(0x68080)
408 # define TV_VADAPT_MODE_LEAST (0 << 26)
421 # define TV_HSCALE_FRAC_MASK 0x00003fff
422 # define TV_HSCALE_FRAC_SHIFT 0
424 #define TV_FILTER_CTL_2 _MMIO(0x68084)
430 # define TV_VSCALE_INT_MASK 0x00038000
437 # define TV_VSCALE_FRAC_MASK 0x00007fff
438 # define TV_VSCALE_FRAC_SHIFT 0
440 #define TV_FILTER_CTL_3 _MMIO(0x68088)
448 # define TV_VSCALE_IP_INT_MASK 0x00038000
457 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
458 # define TV_VSCALE_IP_FRAC_SHIFT 0
460 #define TV_CC_CONTROL _MMIO(0x68090)
465 * CC data is usually sent in field 0.
470 # define TV_CC_HOFF_MASK 0x03ff0000
473 # define TV_CC_LINE_MASK 0x0000003f
474 # define TV_CC_LINE_SHIFT 0
476 #define TV_CC_DATA _MMIO(0x68094)
479 # define TV_CC_DATA_2_MASK 0x007f0000
482 # define TV_CC_DATA_1_MASK 0x0000007f
483 # define TV_CC_DATA_1_SHIFT 0
485 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
486 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
487 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
488 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */