65 	u8 phy_fia_idx;  member
278 	lane_mask &= DP_LANE_ASSIGNMENT_MASK(tc->phy_fia_idx);  in intel_tc_port_get_lane_mask()
279 	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(tc->phy_fia_idx);  in intel_tc_port_get_lane_mask()
293 	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx)) >>  in intel_tc_port_get_pin_assignment_mask()
294 	       DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);  in intel_tc_port_get_pin_assignment_mask()
405 	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc->phy_fia_idx);  in intel_tc_port_set_fia_lane_count()
410 			DFLEXDPMLE1_DPMLETC_ML3(tc->phy_fia_idx) :  in intel_tc_port_set_fia_lane_count()
411 			DFLEXDPMLE1_DPMLETC_ML0(tc->phy_fia_idx);  in intel_tc_port_set_fia_lane_count()
415 			DFLEXDPMLE1_DPMLETC_ML3_2(tc->phy_fia_idx) :  in intel_tc_port_set_fia_lane_count()
416 			DFLEXDPMLE1_DPMLETC_ML1_0(tc->phy_fia_idx);  in intel_tc_port_set_fia_lane_count()
419 		val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc->phy_fia_idx);  in intel_tc_port_set_fia_lane_count()
466 		tc->phy_fia_idx = tc_port % 2;  in tc_phy_load_fia_params()
469 		tc->phy_fia_idx = tc_port;  in tc_phy_load_fia_params()
511 	if (fia_isr & TC_LIVE_STATE_TBT(tc->phy_fia_idx))  in icl_tc_phy_hpd_live_status()
513 	if (fia_isr & TC_LIVE_STATE_TC(tc->phy_fia_idx))  in icl_tc_phy_hpd_live_status()
545 	return val & DP_PHY_MODE_STATUS_COMPLETED(tc->phy_fia_idx);  in icl_tc_phy_is_ready()
565 	val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);  in icl_tc_phy_take_ownership()
567 		val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);  in icl_tc_phy_take_ownership()
589 	return val & DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);  in icl_tc_phy_is_owned()