Lines Matching refs:REG_GENMASK
14 #define EXITLINE_MASK REG_GENMASK(12, 0)
31 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25)
36 #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20)
38 #define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16)
45 #define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8)
50 #define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6)
52 #define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4)
57 #define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
73 #define TGL_PSR_MASK REG_GENMASK(2, 0)
105 #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29)
113 #define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26)
117 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK REG_GENMASK(24, 20)
118 #define EDP_PSR_STATUS_COUNT_MASK REG_GENMASK(19, 16)
124 #define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0)
130 #define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0)
165 #define EDP_MAX_SU_DISABLE_TIME_MASK REG_GENMASK(24, 20)
167 #define EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(14, 13)
171 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(15, 13)
175 #define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13)
179 #define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11)
183 #define TGL_EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 10)
187 #define EDP_PSR2_TP2_TIME_MASK REG_GENMASK(9, 8)
192 #define EDP_PSR2_FRAME_BEFORE_SU_MASK REG_GENMASK(7, 4)
194 #define EDP_PSR2_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
223 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
238 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
240 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
245 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
247 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
268 #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(23, 21)
274 #define ALPM_CTL_ALPM_ENTRY_CHECK_MASK REG_GENMASK(19, 16)
276 #define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK REG_GENMASK(13, 8)
279 #define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0)
284 #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24)
286 #define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16)
288 #define ALPM_CTL2_NUMBER_OF_LTTPR_MASK REG_GENMASK(15, 12)
290 #define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(10, 8)
293 #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK REG_GENMASK(2, 0)
300 #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20)
302 #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16)
304 #define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0)
311 #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24)
314 #define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(20, 16)
316 #define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(12, 8)
318 #define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(4, 0)