Lines Matching +full:hpd +full:- +full:reliable +full:- +full:delay
49 * Since Haswell Display controller supports Panel Self-Refresh on display
63 * The implementation uses the hardware-based PSR support which automatically
64 * enters/exits self-refresh mode. The hardware takes care of sending the
67 * changes to know when to exit self-refresh mode again. Unfortunately that
72 * issues the self-refresh re-enable code is done from a work queue, which
80 * entry/exit allows the HW to enter a low-power state even when page flipping
96 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
160 * In standby mode (as opposed to link-off) this makes no difference
174 * The rest of the bits are more self-explanatory and/or
194 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
195 (intel_dp)->psr.source_support)
199 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) in intel_encoder_can_psr()
211 * the output is enabled. For non-eDP outputs the main link is always in intel_psr_needs_aux_io_power()
212 * on, hence it doesn't require the HW initiated AUX wake-up signaling used in intel_psr_needs_aux_io_power()
216 * - Consider leaving AUX IO disabled for eDP / PR as well, in case in intel_psr_needs_aux_io_power()
217 * the ALPM with main-link off mode is not enabled. in intel_psr_needs_aux_io_power()
218 * - Leave AUX IO enabled for DP / PR, once support for ALPM with in intel_psr_needs_aux_io_power()
219 * main-link off mode is added for it and this mode gets enabled. in intel_psr_needs_aux_io_power()
228 struct intel_connector *connector = intel_dp->attached_connector; in psr_global_enabled()
230 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
232 if (display->params.enable_psr == -1) in psr_global_enabled()
233 return connector->panel.vbt.psr.enable; in psr_global_enabled()
234 return display->params.enable_psr; in psr_global_enabled()
246 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr2_global_enabled()
251 if (display->params.enable_psr == 1) in psr2_global_enabled()
261 if (display->params.enable_psr != -1) in psr2_su_region_et_global_enabled()
271 if ((display->params.enable_psr != -1) || in panel_replay_global_enabled()
272 (intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE)) in panel_replay_global_enabled()
282 EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_irq_psr_error_bit_get()
290 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); in psr_irq_post_exit_bit_get()
298 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); in psr_irq_pre_entry_bit_get()
306 EDP_PSR_MASK(intel_dp->psr.transcoder); in psr_irq_mask_get()
384 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_irq_control()
387 if (intel_dp->psr.panel_replay_enabled) in psr_irq_control()
391 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
402 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); in psr_event_print()
404 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); in psr_event_print()
406 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); in psr_event_print()
408 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); in psr_event_print()
410 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); in psr_event_print()
412 drm_dbg_kms(display->drm, "\tGraphics reset\n"); in psr_event_print()
414 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); in psr_event_print()
416 drm_dbg_kms(display->drm, "\tMemory up\n"); in psr_event_print()
418 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); in psr_event_print()
420 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); in psr_event_print()
422 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); in psr_event_print()
424 drm_dbg_kms(display->drm, "\tRegister updated\n"); in psr_event_print()
426 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); in psr_event_print()
428 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); in psr_event_print()
430 drm_dbg_kms(display->drm, "\tVBI enabled\n"); in psr_event_print()
432 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); in psr_event_print()
434 drm_dbg_kms(display->drm, "\tPSR disabled\n"); in psr_event_print()
440 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_irq_handler()
441 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
445 intel_dp->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
446 drm_dbg_kms(display->drm, in intel_psr_irq_handler()
452 intel_dp->psr.last_exit = time_ns; in intel_psr_irq_handler()
453 drm_dbg_kms(display->drm, in intel_psr_irq_handler()
464 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); in intel_psr_irq_handler()
469 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", in intel_psr_irq_handler()
472 intel_dp->psr.irq_aux_error = true; in intel_psr_irq_handler()
485 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in intel_psr_irq_handler()
494 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_get_sink_sync_latency()
498 drm_dbg_kms(display->drm, in intel_dp_get_sink_sync_latency()
507 if (intel_dp->psr.sink_panel_replay_su_support) in intel_dp_get_su_capability()
508 drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_get_su_capability()
512 su_capability = intel_dp->psr_dpcd[1]; in intel_dp_get_su_capability()
520 return intel_dp->psr.sink_panel_replay_su_support ? in intel_dp_get_su_x_granularity_offset()
528 return intel_dp->psr.sink_panel_replay_su_support ? in intel_dp_get_su_y_granularity_offset()
561 r = drm_dp_dpcd_read(&intel_dp->aux, in intel_dp_get_su_granularity()
565 drm_dbg_kms(display->drm, in intel_dp_get_su_granularity()
574 r = drm_dp_dpcd_read(&intel_dp->aux, in intel_dp_get_su_granularity()
578 drm_dbg_kms(display->drm, in intel_dp_get_su_granularity()
586 intel_dp->psr.su_w_granularity = w; in intel_dp_get_su_granularity()
587 intel_dp->psr.su_y_granularity = y; in intel_dp_get_su_granularity()
596 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
597 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); in _panel_replay_init_dpcd()
601 if (!(intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { in _panel_replay_init_dpcd()
602 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
608 intel_dp->psr.sink_panel_replay_support = true; in _panel_replay_init_dpcd()
610 if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) in _panel_replay_init_dpcd()
611 intel_dp->psr.sink_panel_replay_su_support = true; in _panel_replay_init_dpcd()
613 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
615 intel_dp->psr.sink_panel_replay_su_support ? in _panel_replay_init_dpcd()
623 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", in _psr_init_dpcd()
624 intel_dp->psr_dpcd[0]); in _psr_init_dpcd()
626 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { in _psr_init_dpcd()
627 drm_dbg_kms(display->drm, in _psr_init_dpcd()
632 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { in _psr_init_dpcd()
633 drm_dbg_kms(display->drm, in _psr_init_dpcd()
638 intel_dp->psr.sink_support = true; in _psr_init_dpcd()
639 intel_dp->psr.sink_sync_latency = in _psr_init_dpcd()
643 intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { in _psr_init_dpcd()
644 bool y_req = intel_dp->psr_dpcd[1] & in _psr_init_dpcd()
649 * Y-coordinate) can handle Y-coordinates in VSC but we are in _psr_init_dpcd()
655 * Y-coordinate requirement panels we would need to enable in _psr_init_dpcd()
658 intel_dp->psr.sink_psr2_support = y_req && in _psr_init_dpcd()
660 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", in _psr_init_dpcd()
661 intel_dp->psr.sink_psr2_support ? "" : "not "); in _psr_init_dpcd()
667 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, in intel_psr_init_dpcd()
668 sizeof(intel_dp->psr_dpcd)); in intel_psr_init_dpcd()
669 drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, in intel_psr_init_dpcd()
670 &intel_dp->pr_dpcd); in intel_psr_init_dpcd()
672 if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT) in intel_psr_init_dpcd()
675 if (intel_dp->psr_dpcd[0]) in intel_psr_init_dpcd()
678 if (intel_dp->psr.sink_psr2_support || in intel_psr_init_dpcd()
679 intel_dp->psr.sink_panel_replay_su_support) in intel_psr_init_dpcd()
686 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_psr_setup_aux()
687 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_psr_setup_aux()
694 [3] = 1 - 1, in hsw_psr_setup_aux()
703 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); in hsw_psr_setup_aux()
705 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); in hsw_psr_setup_aux()
708 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), in hsw_psr_setup_aux()
726 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) in psr2_su_region_et_valid()
730 intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : in psr2_su_region_et_valid()
731 intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && in psr2_su_region_et_valid()
745 if (crtc_state->has_sel_update) in _panel_replay_enable_sink()
748 if (crtc_state->enable_psr2_su_region_et) in _panel_replay_enable_sink()
751 if (crtc_state->req_psr2_sdp_prior_scanline) in _panel_replay_enable_sink()
755 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); in _panel_replay_enable_sink()
757 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, in _panel_replay_enable_sink()
767 if (crtc_state->has_sel_update) { in _psr_enable_sink()
770 if (intel_dp->psr.link_standby) in _psr_enable_sink()
777 if (crtc_state->req_psr2_sdp_prior_scanline) in _psr_enable_sink()
780 if (crtc_state->enable_psr2_su_region_et) in _psr_enable_sink()
783 if (intel_dp->psr.entry_setup_frames > 0) in _psr_enable_sink()
786 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); in _psr_enable_sink()
798 if (!intel_dp_is_edp(intel_dp) || (!crtc_state->has_panel_replay && in intel_psr_enable_sink_alpm()
799 !crtc_state->has_sel_update)) in intel_psr_enable_sink_alpm()
804 if (crtc_state->has_panel_replay) in intel_psr_enable_sink_alpm()
807 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); in intel_psr_enable_sink_alpm()
815 crtc_state->has_panel_replay ? in intel_psr_enable_sink()
820 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_enable_sink()
826 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr1_get_tp_time()
827 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr1_get_tp_time()
833 if (display->params.psr_safest_params) { in intel_psr1_get_tp_time()
839 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) in intel_psr1_get_tp_time()
841 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
843 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
848 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
850 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
852 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
862 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && in intel_psr1_get_tp_time()
863 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
868 drm_dp_tps3_supported(intel_dp->dpcd)) in intel_psr1_get_tp_time()
879 struct intel_connector *connector = intel_dp->attached_connector; in psr_compute_idle_frames()
883 * off-by-one issue that HW has in some cases. in psr_compute_idle_frames()
885 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); in psr_compute_idle_frames()
886 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); in psr_compute_idle_frames()
888 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) in psr_compute_idle_frames()
897 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_activate_psr1()
898 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr1()
910 if (intel_dp->psr.link_standby) in hsw_activate_psr1()
919 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); in hsw_activate_psr1()
928 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr2_get_tp_time()
931 if (display->params.psr_safest_params) in intel_psr2_get_tp_time()
934 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && in intel_psr2_get_tp_time()
935 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) in intel_psr2_get_tp_time()
937 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) in intel_psr2_get_tp_time()
939 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) in intel_psr2_get_tp_time()
949 return intel_dp->alpm_parameters.io_wake_lines < 9 && in psr2_block_count_lines()
950 intel_dp->alpm_parameters.fast_wake_lines < 9 ? 8 : 12; in psr2_block_count_lines()
963 intel_dp->psr.sink_sync_latency + 1, in frames_before_su_entry()
967 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) in frames_before_su_entry()
968 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; in frames_before_su_entry()
976 struct intel_psr *psr = &intel_dp->psr; in dg2_activate_panel_replay()
977 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in dg2_activate_panel_replay()
979 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { in dg2_activate_panel_replay()
980 u32 val = psr->su_region_et_enabled ? in dg2_activate_panel_replay()
983 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in dg2_activate_panel_replay()
991 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), in dg2_activate_panel_replay()
994 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, in dg2_activate_panel_replay()
1001 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_activate_psr2()
1002 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr2()
1025 /* Wa_22012278275:adl-p */ in hsw_activate_psr2()
1043 tmp = map[intel_dp->alpm_parameters.io_wake_lines - in hsw_activate_psr2()
1047 tmp = map[intel_dp->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; in hsw_activate_psr2()
1050 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); in hsw_activate_psr2()
1052 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); in hsw_activate_psr2()
1053 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines); in hsw_activate_psr2()
1055 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); in hsw_activate_psr2()
1056 val |= EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines); in hsw_activate_psr2()
1059 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in hsw_activate_psr2()
1063 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); in hsw_activate_psr2()
1065 if (intel_dp->psr.psr2_sel_fetch_enabled) { in hsw_activate_psr2()
1070 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); in hsw_activate_psr2()
1076 if (intel_dp->psr.su_region_et_enabled) in hsw_activate_psr2()
1091 struct drm_i915_private *dev_priv = to_i915(display->drm); in transcoder_has_psr2()
1105 if (!crtc_state->hw.active) in intel_get_frame_time_us()
1109 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); in intel_get_frame_time_us()
1116 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr2_program_idle_frames()
1126 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_psr2_enable_dc3co()
1135 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_psr2_disable_dc3co()
1146 mutex_lock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
1148 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) in tgl_dc3co_disable_work()
1153 mutex_unlock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
1158 if (!intel_dp->psr.dc3co_exitline) in tgl_disallow_dc3co_on_psr2_exit()
1161 cancel_delayed_work(&intel_dp->psr.dc3co_work); in tgl_disallow_dc3co_on_psr2_exit()
1172 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dc3co_is_pipe_port_compatible()
1173 struct drm_i915_private *dev_priv = to_i915(display->drm); in dc3co_is_pipe_port_compatible()
1174 enum port port = dig_port->base.port; in dc3co_is_pipe_port_compatible()
1187 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_dc3co_exitline_compute_config()
1188 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; in tgl_dc3co_exitline_compute_config()
1189 struct i915_power_domains *power_domains = &display->power.domains; in tgl_dc3co_exitline_compute_config()
1203 if (crtc_state->enable_psr2_sel_fetch) in tgl_dc3co_exitline_compute_config()
1206 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) in tgl_dc3co_exitline_compute_config()
1212 /* Wa_16011303918:adl-p */ in tgl_dc3co_exitline_compute_config()
1221 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; in tgl_dc3co_exitline_compute_config()
1223 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) in tgl_dc3co_exitline_compute_config()
1226 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; in tgl_dc3co_exitline_compute_config()
1234 if (!display->params.enable_psr2_sel_fetch && in intel_psr2_sel_fetch_config_valid()
1235 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { in intel_psr2_sel_fetch_config_valid()
1236 drm_dbg_kms(display->drm, in intel_psr2_sel_fetch_config_valid()
1241 if (crtc_state->uapi.async_flip) { in intel_psr2_sel_fetch_config_valid()
1242 drm_dbg_kms(display->drm, in intel_psr2_sel_fetch_config_valid()
1247 return crtc_state->enable_psr2_sel_fetch = true; in intel_psr2_sel_fetch_config_valid()
1254 struct drm_i915_private *dev_priv = to_i915(display->drm); in psr2_granularity_check()
1255 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check()
1256 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in psr2_granularity_check()
1257 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in psr2_granularity_check()
1261 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) in psr2_granularity_check()
1264 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) in psr2_granularity_check()
1268 if (!crtc_state->enable_psr2_sel_fetch) in psr2_granularity_check()
1269 return intel_dp->psr.su_y_granularity == 4; in psr2_granularity_check()
1277 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
1278 else if (intel_dp->psr.su_y_granularity <= 2) in psr2_granularity_check()
1280 else if ((intel_dp->psr.su_y_granularity % 4) == 0) in psr2_granularity_check()
1281 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
1286 if (crtc_state->dsc.compression_enable && in psr2_granularity_check()
1287 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()
1290 crtc_state->su_y_granularity = y_granularity; in psr2_granularity_check()
1298 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; in _compute_psr2_sdp_prior_scanline_indication()
1301 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; in _compute_psr2_sdp_prior_scanline_indication()
1302 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); in _compute_psr2_sdp_prior_scanline_indication()
1305 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
1307 if ((hblank_ns - req_ns) > 100) in _compute_psr2_sdp_prior_scanline_indication()
1310 /* Not supported <13 / Wa_22012279113:adl-p */ in _compute_psr2_sdp_prior_scanline_indication()
1311 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) in _compute_psr2_sdp_prior_scanline_indication()
1314 crtc_state->req_psr2_sdp_prior_scanline = true; in _compute_psr2_sdp_prior_scanline_indication()
1322 int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); in intel_psr_entry_setup_frames()
1326 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1328 intel_dp->psr_dpcd[1]); in intel_psr_entry_setup_frames()
1329 return -ETIME; in intel_psr_entry_setup_frames()
1333 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { in intel_psr_entry_setup_frames()
1337 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1341 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1344 return -ETIME; in intel_psr_entry_setup_frames()
1356 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - in wake_lines_fit_into_vblank()
1357 crtc_state->hw.adjusted_mode.crtc_vblank_start; in wake_lines_fit_into_vblank()
1361 wake_lines = intel_dp->alpm_parameters.aux_less_wake_lines; in wake_lines_fit_into_vblank()
1365 intel_dp->alpm_parameters.io_wake_lines; in wake_lines_fit_into_vblank()
1367 if (crtc_state->req_psr2_sdp_prior_scanline) in wake_lines_fit_into_vblank()
1368 vblank -= 1; in wake_lines_fit_into_vblank()
1384 drm_dbg_kms(display->drm, in alpm_config_valid()
1390 drm_dbg_kms(display->drm, in alpm_config_valid()
1402 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr2_config_valid()
1403 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in intel_psr2_config_valid()
1404 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_psr2_config_valid()
1407 if (!intel_dp->psr.sink_psr2_support) in intel_psr2_config_valid()
1412 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); in intel_psr2_config_valid()
1419 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1425 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1430 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { in intel_psr2_config_valid()
1431 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1433 transcoder_name(crtc_state->cpu_transcoder)); in intel_psr2_config_valid()
1442 if (crtc_state->dsc.compression_enable && in intel_psr2_config_valid()
1444 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1463 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1464 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1466 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
1470 /* Wa_16011303918:adl-p */ in intel_psr2_config_valid()
1471 if (crtc_state->vrr.enable && in intel_psr2_config_valid()
1473 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1481 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
1483 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1503 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1509 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1514 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) in intel_sel_update_config_valid()
1518 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1523 if (crtc_state->has_panel_replay && (DISPLAY_VER(display) < 14 || in intel_sel_update_config_valid()
1524 !intel_dp->psr.sink_panel_replay_su_support)) in intel_sel_update_config_valid()
1527 if (crtc_state->crc_enabled) { in intel_sel_update_config_valid()
1528 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1534 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1539 crtc_state->enable_psr2_su_region_et = in intel_sel_update_config_valid()
1540 psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay); in intel_sel_update_config_valid()
1545 crtc_state->enable_psr2_sel_fetch = false; in intel_sel_update_config_valid()
1553 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in _psr_compute_config()
1560 if (crtc_state->vrr.enable) in _psr_compute_config()
1569 intel_dp->psr.entry_setup_frames = entry_setup_frames; in _psr_compute_config()
1571 drm_dbg_kms(display->drm, in _psr_compute_config()
1586 to_intel_connector(conn_state->connector); in _panel_replay_compute_config()
1587 struct intel_hdcp *hdcp = &connector->hdcp; in _panel_replay_compute_config()
1593 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); in _panel_replay_compute_config()
1604 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1610 if (conn_state->content_protection == in _panel_replay_compute_config()
1612 (conn_state->content_protection == in _panel_replay_compute_config()
1613 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == in _panel_replay_compute_config()
1615 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1623 if (crtc_state->crc_enabled) { in _panel_replay_compute_config()
1624 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1637 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_psr_compute_config()
1640 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); in intel_psr_compute_config()
1644 if (intel_dp->psr.sink_not_reliable) { in intel_psr_compute_config()
1645 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1646 "PSR sink implementation is not reliable\n"); in intel_psr_compute_config()
1650 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_psr_compute_config()
1651 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1661 if (crtc_state->joiner_pipes) { in intel_psr_compute_config()
1662 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1667 crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, in intel_psr_compute_config()
1671 crtc_state->has_psr = crtc_state->has_panel_replay ? true : in intel_psr_compute_config()
1674 if (!crtc_state->has_psr) in intel_psr_compute_config()
1677 crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
1685 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_psr_get_config()
1692 intel_dp = &dig_port->dp; in intel_psr_get_config()
1696 mutex_lock(&intel_dp->psr.lock); in intel_psr_get_config()
1697 if (!intel_dp->psr.enabled) in intel_psr_get_config()
1700 if (intel_dp->psr.panel_replay_enabled) { in intel_psr_get_config()
1701 pipe_config->has_psr = pipe_config->has_panel_replay = true; in intel_psr_get_config()
1707 pipe_config->has_psr = true; in intel_psr_get_config()
1710 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; in intel_psr_get_config()
1711 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_get_config()
1713 if (!intel_dp->psr.sel_update_enabled) in intel_psr_get_config()
1720 pipe_config->enable_psr2_sel_fetch = true; in intel_psr_get_config()
1723 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; in intel_psr_get_config()
1728 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); in intel_psr_get_config()
1731 mutex_unlock(&intel_dp->psr.lock); in intel_psr_get_config()
1737 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_activate()
1739 drm_WARN_ON(display->drm, in intel_psr_activate()
1743 drm_WARN_ON(display->drm, in intel_psr_activate()
1746 drm_WARN_ON(display->drm, intel_dp->psr.active); in intel_psr_activate()
1748 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_activate()
1750 /* psr1, psr2 and panel-replay are mutually exclusive.*/ in intel_psr_activate()
1751 if (intel_dp->psr.panel_replay_enabled) in intel_psr_activate()
1753 else if (intel_dp->psr.sel_update_enabled) in intel_psr_activate()
1758 intel_dp->psr.active = true; in intel_psr_activate()
1763 switch (intel_dp->psr.pipe) { in wa_16013835468_bit_get()
1773 MISSING_CASE(intel_dp->psr.pipe); in wa_16013835468_bit_get()
1790 set_wa_bit |= crtc_state->wm_level_disabled; in wm_optimization_wa()
1794 set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start != in wm_optimization_wa()
1795 crtc_state->hw.adjusted_mode.crtc_vdisplay; in wm_optimization_wa()
1809 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_enable_source()
1810 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1821 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also in intel_psr_enable_source()
1841 * For some unknown reason on HSW non-ULT (or at least on in intel_psr_enable_source()
1874 if (intel_dp->psr.dc3co_exitline) in intel_psr_enable_source()
1878 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); in intel_psr_enable_source()
1882 intel_dp->psr.psr2_sel_fetch_enabled ? in intel_psr_enable_source()
1894 if (intel_dp->psr.sel_update_enabled) { in intel_psr_enable_source()
1902 * All supported adlp panels have 1-based X granularity, this may in intel_psr_enable_source()
1903 * cause issues if non-supported panels are used. in intel_psr_enable_source()
1905 if (!intel_dp->psr.panel_replay_enabled && in intel_psr_enable_source()
1912 if (!intel_dp->psr.panel_replay_enabled && in intel_psr_enable_source()
1927 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_interrupt_error_check()
1930 if (intel_dp->psr.panel_replay_enabled) in psr_interrupt_error_check()
1944 intel_dp->psr.sink_not_reliable = true; in psr_interrupt_error_check()
1945 drm_dbg_kms(display->drm, in psr_interrupt_error_check()
1961 drm_WARN_ON(display->drm, intel_dp->psr.enabled); in intel_psr_enable_locked()
1963 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; in intel_psr_enable_locked()
1964 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; in intel_psr_enable_locked()
1965 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_enable_locked()
1966 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1967 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1970 intel_dp->psr.dc3co_exit_delay = val; in intel_psr_enable_locked()
1971 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1972 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1973 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; in intel_psr_enable_locked()
1974 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_enable_locked()
1975 intel_dp->psr.req_psr2_sdp_prior_scanline = in intel_psr_enable_locked()
1976 crtc_state->req_psr2_sdp_prior_scanline; in intel_psr_enable_locked()
1981 if (intel_dp->psr.panel_replay_enabled) { in intel_psr_enable_locked()
1982 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); in intel_psr_enable_locked()
1984 drm_dbg_kms(display->drm, "Enabling PSR%s\n", in intel_psr_enable_locked()
1985 intel_dp->psr.sel_update_enabled ? "2" : "1"); in intel_psr_enable_locked()
1995 intel_snps_phy_update_psr_power_state(&dig_port->base, true); in intel_psr_enable_locked()
1998 intel_dp->psr.enabled = true; in intel_psr_enable_locked()
1999 intel_dp->psr.paused = false; in intel_psr_enable_locked()
2007 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_exit()
2010 if (!intel_dp->psr.active) { in intel_psr_exit()
2014 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); in intel_psr_exit()
2019 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); in intel_psr_exit()
2024 if (intel_dp->psr.panel_replay_enabled) { in intel_psr_exit()
2025 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), in intel_psr_exit()
2027 } else if (intel_dp->psr.sel_update_enabled) { in intel_psr_exit()
2034 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); in intel_psr_exit()
2040 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); in intel_psr_exit()
2042 intel_dp->psr.active = false; in intel_psr_exit()
2048 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_wait_exit_locked()
2052 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || in intel_psr_wait_exit_locked()
2053 intel_dp->psr.panel_replay_enabled)) { in intel_psr_wait_exit_locked()
2064 drm_err(display->drm, "Timed out waiting PSR idle state\n"); in intel_psr_wait_exit_locked()
2070 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_disable_locked()
2071 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_disable_locked()
2073 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_disable_locked()
2075 if (!intel_dp->psr.enabled) in intel_psr_disable_locked()
2078 if (intel_dp->psr.panel_replay_enabled) in intel_psr_disable_locked()
2079 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); in intel_psr_disable_locked()
2081 drm_dbg_kms(display->drm, "Disabling PSR%s\n", in intel_psr_disable_locked()
2082 intel_dp->psr.sel_update_enabled ? "2" : "1"); in intel_psr_disable_locked()
2095 if (intel_dp->psr.sel_update_enabled) { in intel_psr_disable_locked()
2097 if (!intel_dp->psr.panel_replay_enabled && in intel_psr_disable_locked()
2108 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); in intel_psr_disable_locked()
2111 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { in intel_psr_disable_locked()
2122 if (!intel_dp->psr.panel_replay_enabled) { in intel_psr_disable_locked()
2123 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); in intel_psr_disable_locked()
2125 if (intel_dp->psr.sel_update_enabled) in intel_psr_disable_locked()
2126 drm_dp_dpcd_writeb(&intel_dp->aux, in intel_psr_disable_locked()
2130 intel_dp->psr.enabled = false; in intel_psr_disable_locked()
2131 intel_dp->psr.panel_replay_enabled = false; in intel_psr_disable_locked()
2132 intel_dp->psr.sel_update_enabled = false; in intel_psr_disable_locked()
2133 intel_dp->psr.psr2_sel_fetch_enabled = false; in intel_psr_disable_locked()
2134 intel_dp->psr.su_region_et_enabled = false; in intel_psr_disable_locked()
2135 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_disable_locked()
2139 * intel_psr_disable - Disable PSR
2150 if (!old_crtc_state->has_psr) in intel_psr_disable()
2153 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp))) in intel_psr_disable()
2156 mutex_lock(&intel_dp->psr.lock); in intel_psr_disable()
2160 mutex_unlock(&intel_dp->psr.lock); in intel_psr_disable()
2161 cancel_work_sync(&intel_dp->psr.work); in intel_psr_disable()
2162 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); in intel_psr_disable()
2166 * intel_psr_pause - Pause PSR
2174 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pause()
2179 mutex_lock(&psr->lock); in intel_psr_pause()
2181 if (!psr->enabled) { in intel_psr_pause()
2182 mutex_unlock(&psr->lock); in intel_psr_pause()
2187 drm_WARN_ON(display->drm, psr->paused); in intel_psr_pause()
2191 psr->paused = true; in intel_psr_pause()
2193 mutex_unlock(&psr->lock); in intel_psr_pause()
2195 cancel_work_sync(&psr->work); in intel_psr_pause()
2196 cancel_delayed_work_sync(&psr->dc3co_work); in intel_psr_pause()
2200 * intel_psr_resume - Resume PSR
2207 struct intel_psr *psr = &intel_dp->psr; in intel_psr_resume()
2212 mutex_lock(&psr->lock); in intel_psr_resume()
2214 if (!psr->paused) in intel_psr_resume()
2217 psr->paused = false; in intel_psr_resume()
2221 mutex_unlock(&psr->lock); in intel_psr_resume()
2226 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_enable_bit_get()
2234 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_single_full_frame_bit_get()
2243 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_partial_frame_bit_get()
2252 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_continuos_full_frame()
2262 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_force_hw_tracking_exit()
2264 if (intel_dp->psr.psr2_sel_fetch_enabled) in psr_force_hw_tracking_exit()
2276 * instead of disabling and re-enabling. in psr_force_hw_tracking_exit()
2285 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); in psr_force_hw_tracking_exit()
2291 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_psr2_program_trans_man_trk_ctl()
2292 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_psr2_program_trans_man_trk_ctl()
2295 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_trans_man_trk_ctl()
2298 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr2_program_trans_man_trk_ctl()
2299 crtc_state->uapi.encoder_mask) { in intel_psr2_program_trans_man_trk_ctl()
2302 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr2_program_trans_man_trk_ctl()
2303 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) in intel_psr2_program_trans_man_trk_ctl()
2309 crtc_state->psr2_man_track_ctl); in intel_psr2_program_trans_man_trk_ctl()
2311 if (!crtc_state->enable_psr2_su_region_et) in intel_psr2_program_trans_man_trk_ctl()
2314 intel_de_write(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), in intel_psr2_program_trans_man_trk_ctl()
2315 crtc_state->pipe_srcsz_early_tpt); in intel_psr2_program_trans_man_trk_ctl()
2322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in psr2_man_trk_ctl_calc()
2323 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in psr2_man_trk_ctl_calc()
2335 if (crtc_state->psr2_su_area.y1 == -1) in psr2_man_trk_ctl_calc()
2339 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); in psr2_man_trk_ctl_calc()
2340 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); in psr2_man_trk_ctl_calc()
2342 drm_WARN_ON(crtc_state->uapi.crtc->dev, in psr2_man_trk_ctl_calc()
2343 crtc_state->psr2_su_area.y1 % 4 || in psr2_man_trk_ctl_calc()
2344 crtc_state->psr2_su_area.y2 % 4); in psr2_man_trk_ctl_calc()
2347 crtc_state->psr2_su_area.y1 / 4 + 1); in psr2_man_trk_ctl_calc()
2349 crtc_state->psr2_su_area.y2 / 4 + 1); in psr2_man_trk_ctl_calc()
2352 crtc_state->psr2_man_track_ctl = val; in psr2_man_trk_ctl_calc()
2360 if (!crtc_state->enable_psr2_su_region_et || full_update) in psr2_pipe_srcsz_early_tpt_calc()
2363 width = drm_rect_width(&crtc_state->psr2_su_area); in psr2_pipe_srcsz_early_tpt_calc()
2364 height = drm_rect_height(&crtc_state->psr2_su_area); in psr2_pipe_srcsz_early_tpt_calc()
2366 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); in psr2_pipe_srcsz_early_tpt_calc()
2376 if (overlap_damage_area->y1 == -1) { in clip_area_update()
2377 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
2378 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
2382 if (damage_area->y1 < overlap_damage_area->y1) in clip_area_update()
2383 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
2385 if (damage_area->y2 > overlap_damage_area->y2) in clip_area_update()
2386 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
2392 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_sel_fetch_pipe_alignment()
2393 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment()
2397 if (crtc_state->dsc.compression_enable && in intel_psr2_sel_fetch_pipe_alignment()
2399 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
2401 y_alignment = crtc_state->su_y_granularity; in intel_psr2_sel_fetch_pipe_alignment()
2403 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; in intel_psr2_sel_fetch_pipe_alignment()
2404 if (crtc_state->psr2_su_area.y2 % y_alignment) in intel_psr2_sel_fetch_pipe_alignment()
2405 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / in intel_psr2_sel_fetch_pipe_alignment()
2423 if (!crtc_state->enable_psr2_su_region_et) in intel_psr2_sel_fetch_et_alignment()
2429 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_et_alignment()
2432 if (plane->id != PLANE_CURSOR) in intel_psr2_sel_fetch_et_alignment()
2435 if (!new_plane_state->uapi.visible) in intel_psr2_sel_fetch_et_alignment()
2438 inter = crtc_state->psr2_su_area; in intel_psr2_sel_fetch_et_alignment()
2439 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) in intel_psr2_sel_fetch_et_alignment()
2442 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, in intel_psr2_sel_fetch_et_alignment()
2443 &crtc_state->pipe_src); in intel_psr2_sel_fetch_et_alignment()
2459 if (plane_state->uapi.dst.y1 < 0 || in psr2_sel_fetch_plane_state_supported()
2460 plane_state->uapi.dst.x1 < 0 || in psr2_sel_fetch_plane_state_supported()
2461 plane_state->scaler_id >= 0 || in psr2_sel_fetch_plane_state_supported()
2462 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) in psr2_sel_fetch_plane_state_supported()
2477 if (crtc_state->scaler_state.scaler_id >= 0) in psr2_sel_fetch_pipe_state_supported()
2487 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_psr2_sel_fetch_update()
2494 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_sel_fetch_update()
2502 crtc_state->psr2_su_area.x1 = 0; in intel_psr2_sel_fetch_update()
2503 crtc_state->psr2_su_area.y1 = -1; in intel_psr2_sel_fetch_update()
2504 crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2505 crtc_state->psr2_su_area.y2 = -1; in intel_psr2_sel_fetch_update()
2515 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, in intel_psr2_sel_fetch_update()
2518 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_update()
2521 if (!new_plane_state->uapi.visible && in intel_psr2_sel_fetch_update()
2522 !old_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2535 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || in intel_psr2_sel_fetch_update()
2536 !drm_rect_equals(&new_plane_state->uapi.dst, in intel_psr2_sel_fetch_update()
2537 &old_plane_state->uapi.dst)) { in intel_psr2_sel_fetch_update()
2538 if (old_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2539 damaged_area.y1 = old_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2540 damaged_area.y2 = old_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2541 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, in intel_psr2_sel_fetch_update()
2542 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2545 if (new_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2546 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2547 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2548 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, in intel_psr2_sel_fetch_update()
2549 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2552 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { in intel_psr2_sel_fetch_update()
2554 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2555 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2556 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, in intel_psr2_sel_fetch_update()
2557 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2561 src = drm_plane_state_src(&new_plane_state->uapi); in intel_psr2_sel_fetch_update()
2564 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, in intel_psr2_sel_fetch_update()
2565 &new_plane_state->uapi, &damaged_area)) in intel_psr2_sel_fetch_update()
2568 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2569 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2570 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2571 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2573 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2582 if (crtc_state->psr2_su_area.y1 == -1) { in intel_psr2_sel_fetch_update()
2583 drm_info_once(display->drm, in intel_psr2_sel_fetch_update()
2585 pipe_name(crtc->pipe)); in intel_psr2_sel_fetch_update()
2593 if (!crtc_state->has_panel_replay && in intel_psr2_sel_fetch_update()
2596 crtc_state->splitter.enable) in intel_psr2_sel_fetch_update()
2597 crtc_state->psr2_su_area.y1 = 0; in intel_psr2_sel_fetch_update()
2599 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_psr2_sel_fetch_update()
2620 struct intel_plane *linked = new_plane_state->planar_linked_plane; in intel_psr2_sel_fetch_update()
2622 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || in intel_psr2_sel_fetch_update()
2623 !new_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2626 inter = crtc_state->psr2_su_area; in intel_psr2_sel_fetch_update()
2627 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2628 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { in intel_psr2_sel_fetch_update()
2629 sel_fetch_area->y1 = -1; in intel_psr2_sel_fetch_update()
2630 sel_fetch_area->y2 = -1; in intel_psr2_sel_fetch_update()
2632 * if plane sel fetch was previously enabled -> in intel_psr2_sel_fetch_update()
2635 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) in intel_psr2_sel_fetch_update()
2636 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
2646 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2647 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2648 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2649 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
2663 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2664 linked_sel_fetch_area->y1 = sel_fetch_area->y1; in intel_psr2_sel_fetch_update()
2665 linked_sel_fetch_area->y2 = sel_fetch_area->y2; in intel_psr2_sel_fetch_update()
2666 crtc_state->update_planes |= BIT(linked->id); in intel_psr2_sel_fetch_update()
2672 crtc_state->pipe_srcsz_early_tpt = in intel_psr2_sel_fetch_update()
2681 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_psr_pre_plane_update()
2691 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in intel_psr_pre_plane_update()
2692 old_crtc_state->uapi.encoder_mask) { in intel_psr_pre_plane_update()
2694 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pre_plane_update()
2697 mutex_lock(&psr->lock); in intel_psr_pre_plane_update()
2701 * - PSR disabled in new state in intel_psr_pre_plane_update()
2702 * - All planes will go inactive in intel_psr_pre_plane_update()
2703 * - Changing between PSR versions in intel_psr_pre_plane_update()
2704 * - Region Early Transport changing in intel_psr_pre_plane_update()
2705 * - Display WA #1136: skl, bxt in intel_psr_pre_plane_update()
2708 needs_to_disable |= !new_crtc_state->has_psr; in intel_psr_pre_plane_update()
2709 needs_to_disable |= !new_crtc_state->active_planes; in intel_psr_pre_plane_update()
2710 needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled; in intel_psr_pre_plane_update()
2711 needs_to_disable |= new_crtc_state->enable_psr2_su_region_et != in intel_psr_pre_plane_update()
2712 psr->su_region_et_enabled; in intel_psr_pre_plane_update()
2714 new_crtc_state->wm_level_disabled; in intel_psr_pre_plane_update()
2716 if (psr->enabled && needs_to_disable) in intel_psr_pre_plane_update()
2718 else if (psr->enabled && new_crtc_state->wm_level_disabled) in intel_psr_pre_plane_update()
2722 mutex_unlock(&psr->lock); in intel_psr_pre_plane_update()
2734 if (!crtc_state->has_psr) in intel_psr_post_plane_update()
2737 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in intel_psr_post_plane_update()
2738 crtc_state->uapi.encoder_mask) { in intel_psr_post_plane_update()
2740 struct intel_psr *psr = &intel_dp->psr; in intel_psr_post_plane_update()
2743 mutex_lock(&psr->lock); in intel_psr_post_plane_update()
2745 drm_WARN_ON(display->drm, in intel_psr_post_plane_update()
2746 psr->enabled && !crtc_state->active_planes); in intel_psr_post_plane_update()
2748 keep_disabled |= psr->sink_not_reliable; in intel_psr_post_plane_update()
2749 keep_disabled |= !crtc_state->active_planes; in intel_psr_post_plane_update()
2753 crtc_state->wm_level_disabled; in intel_psr_post_plane_update()
2755 if (!psr->enabled && !keep_disabled) in intel_psr_post_plane_update()
2757 else if (psr->enabled && !crtc_state->wm_level_disabled) in intel_psr_post_plane_update()
2762 if (crtc_state->crc_enabled && psr->enabled) in intel_psr_post_plane_update()
2767 * invalidate -> flip -> flush sequence. in intel_psr_post_plane_update()
2769 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_post_plane_update()
2771 mutex_unlock(&psr->lock); in intel_psr_post_plane_update()
2778 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr2_ready_for_pipe_update_locked()
2793 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr1_ready_for_pipe_update_locked()
2807 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
2818 if (!new_crtc_state->has_psr) in intel_psr_wait_for_idle_locked()
2821 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_wait_for_idle_locked()
2822 new_crtc_state->uapi.encoder_mask) { in intel_psr_wait_for_idle_locked()
2826 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_wait_for_idle_locked()
2828 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) in intel_psr_wait_for_idle_locked()
2831 if (intel_dp->psr.sel_update_enabled) in intel_psr_wait_for_idle_locked()
2837 drm_err(display->drm, in intel_psr_wait_for_idle_locked()
2845 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in __psr_wait_for_idle_locked()
2850 if (!intel_dp->psr.enabled) in __psr_wait_for_idle_locked()
2853 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || in __psr_wait_for_idle_locked()
2854 intel_dp->psr.panel_replay_enabled)) { in __psr_wait_for_idle_locked()
2862 mutex_unlock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2866 drm_err(display->drm, in __psr_wait_for_idle_locked()
2867 "Timed out waiting for PSR Idle for re-enable\n"); in __psr_wait_for_idle_locked()
2870 mutex_lock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2871 return err == 0 && intel_dp->psr.enabled; in __psr_wait_for_idle_locked()
2882 state = drm_atomic_state_alloc(display->drm); in intel_psr_fastset_force()
2884 return -ENOMEM; in intel_psr_fastset_force()
2888 state->acquire_ctx = &ctx; in intel_psr_fastset_force()
2889 to_intel_atomic_state(state)->internal = true; in intel_psr_fastset_force()
2892 drm_connector_list_iter_begin(display->drm, &conn_iter); in intel_psr_fastset_force()
2897 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) in intel_psr_fastset_force()
2906 if (!conn_state->crtc) in intel_psr_fastset_force()
2909 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); in intel_psr_fastset_force()
2915 /* Mark mode as changed to trigger a pipe->update() */ in intel_psr_fastset_force()
2916 crtc_state->mode_changed = true; in intel_psr_fastset_force()
2923 if (err == -EDEADLK) { in intel_psr_fastset_force()
2950 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); in intel_psr_debug_set()
2951 return -EINVAL; in intel_psr_debug_set()
2954 ret = mutex_lock_interruptible(&intel_dp->psr.lock); in intel_psr_debug_set()
2958 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; in intel_psr_debug_set()
2959 old_disable_bits = intel_dp->psr.debug & in intel_psr_debug_set()
2963 intel_dp->psr.debug = val; in intel_psr_debug_set()
2969 if (intel_dp->psr.enabled) in intel_psr_debug_set()
2972 mutex_unlock(&intel_dp->psr.lock); in intel_psr_debug_set()
2982 struct intel_psr *psr = &intel_dp->psr; in intel_psr_handle_irq()
2985 psr->sink_not_reliable = true; in intel_psr_handle_irq()
2987 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_handle_irq()
2995 mutex_lock(&intel_dp->psr.lock); in intel_psr_work()
2997 if (!intel_dp->psr.enabled) in intel_psr_work()
3000 if (READ_ONCE(intel_dp->psr.irq_aux_error)) in intel_psr_work()
3004 * We have to make sure PSR is ready for re-enable in intel_psr_work()
3007 * and be ready for re-enable. in intel_psr_work()
3017 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) in intel_psr_work()
3022 mutex_unlock(&intel_dp->psr.lock); in intel_psr_work()
3028 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_invalidate_handle()
3030 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_invalidate_handle()
3033 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_invalidate_handle()
3036 CURSURFLIVE(display, intel_dp->psr.pipe), in _psr_invalidate_handle()
3048 CURSURFLIVE(display, intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
3049 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; in _psr_invalidate_handle()
3056 * intel_psr_invalidate - Invalidate PSR
3076 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_psr_invalidate()
3080 mutex_lock(&intel_dp->psr.lock); in intel_psr_invalidate()
3081 if (!intel_dp->psr.enabled) { in intel_psr_invalidate()
3082 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
3087 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_invalidate()
3088 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; in intel_psr_invalidate()
3093 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
3107 struct drm_i915_private *i915 = to_i915(display->drm); in tgl_dc3co_flush_locked()
3109 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || in tgl_dc3co_flush_locked()
3110 !intel_dp->psr.active) in tgl_dc3co_flush_locked()
3114 * At every frontbuffer flush flip event modified delay of delayed work, in tgl_dc3co_flush_locked()
3118 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) in tgl_dc3co_flush_locked()
3122 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work, in tgl_dc3co_flush_locked()
3123 intel_dp->psr.dc3co_exit_delay); in tgl_dc3co_flush_locked()
3129 struct drm_i915_private *dev_priv = to_i915(display->drm); in _psr_flush_handle()
3130 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_flush_handle()
3132 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_flush_handle()
3133 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_flush_handle()
3135 if (intel_dp->psr.busy_frontbuffer_bits == 0) { in _psr_flush_handle()
3151 CURSURFLIVE(display, intel_dp->psr.pipe), in _psr_flush_handle()
3153 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in _psr_flush_handle()
3165 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) in _psr_flush_handle()
3166 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in _psr_flush_handle()
3171 * intel_psr_flush - Flush PSR
3188 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_psr_flush()
3192 mutex_lock(&intel_dp->psr.lock); in intel_psr_flush()
3193 if (!intel_dp->psr.enabled) { in intel_psr_flush()
3194 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
3199 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_flush()
3200 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; in intel_psr_flush()
3207 if (intel_dp->psr.paused) in intel_psr_flush()
3212 !intel_dp->psr.psr2_sel_fetch_enabled)) { in intel_psr_flush()
3223 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
3228 * intel_psr_init - Init basic PSR work and mutex.
3238 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_init()
3239 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr_init()
3254 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { in intel_psr_init()
3255 drm_dbg_kms(display->drm, in intel_psr_init()
3262 intel_dp->psr.source_panel_replay_support = true; in intel_psr_init()
3265 intel_dp->psr.source_support = true; in intel_psr_init()
3270 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; in intel_psr_init()
3272 INIT_WORK(&intel_dp->psr.work, intel_psr_work); in intel_psr_init()
3273 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); in intel_psr_init()
3274 mutex_init(&intel_dp->psr.lock); in intel_psr_init()
3280 struct drm_dp_aux *aux = &intel_dp->aux; in psr_get_status_and_error_status()
3284 offset = intel_dp->psr.panel_replay_enabled ? in psr_get_status_and_error_status()
3291 offset = intel_dp->psr.panel_replay_enabled ? in psr_get_status_and_error_status()
3306 struct drm_dp_aux *aux = &intel_dp->aux; in psr_alpm_check()
3307 struct intel_psr *psr = &intel_dp->psr; in psr_alpm_check()
3311 if (!psr->sel_update_enabled) in psr_alpm_check()
3316 drm_err(display->drm, "Error reading ALPM status\n"); in psr_alpm_check()
3322 psr->sink_not_reliable = true; in psr_alpm_check()
3323 drm_dbg_kms(display->drm, in psr_alpm_check()
3334 struct intel_psr *psr = &intel_dp->psr; in psr_capability_changed_check()
3338 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); in psr_capability_changed_check()
3340 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); in psr_capability_changed_check()
3346 psr->sink_not_reliable = true; in psr_capability_changed_check()
3347 drm_dbg_kms(display->drm, in psr_capability_changed_check()
3351 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); in psr_capability_changed_check()
3365 struct intel_psr *psr = &intel_dp->psr; in intel_psr_short_pulse()
3374 mutex_lock(&psr->lock); in intel_psr_short_pulse()
3376 if (!psr->enabled) in intel_psr_short_pulse()
3380 drm_err(display->drm, in intel_psr_short_pulse()
3385 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || in intel_psr_short_pulse()
3388 psr->sink_not_reliable = true; in intel_psr_short_pulse()
3391 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && in intel_psr_short_pulse()
3393 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3396 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3399 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3402 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3406 drm_err(display->drm, in intel_psr_short_pulse()
3410 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); in intel_psr_short_pulse()
3412 if (!psr->panel_replay_enabled) { in intel_psr_short_pulse()
3418 mutex_unlock(&psr->lock); in intel_psr_short_pulse()
3428 mutex_lock(&intel_dp->psr.lock); in intel_psr_enabled()
3429 ret = intel_dp->psr.enabled; in intel_psr_enabled()
3430 mutex_unlock(&intel_dp->psr.lock); in intel_psr_enabled()
3436 * intel_psr_lock - grab PSR lock
3448 if (!crtc_state->has_psr) in intel_psr_lock()
3451 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_lock()
3452 crtc_state->uapi.encoder_mask) { in intel_psr_lock()
3455 mutex_lock(&intel_dp->psr.lock); in intel_psr_lock()
3461 * intel_psr_unlock - release PSR lock
3471 if (!crtc_state->has_psr) in intel_psr_unlock()
3474 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_unlock()
3475 crtc_state->uapi.encoder_mask) { in intel_psr_unlock()
3478 mutex_unlock(&intel_dp->psr.lock); in intel_psr_unlock()
3487 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_source_status()
3491 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || in psr_source_status()
3492 intel_dp->psr.panel_replay_enabled)) { in psr_source_status()
3535 struct intel_psr *psr = &intel_dp->psr; in intel_psr_sink_capability()
3538 str_yes_no(psr->sink_support)); in intel_psr_sink_capability()
3540 if (psr->sink_support) in intel_psr_sink_capability()
3541 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); in intel_psr_sink_capability()
3542 if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) in intel_psr_sink_capability()
3544 seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); in intel_psr_sink_capability()
3546 str_yes_no(psr->sink_panel_replay_su_support)); in intel_psr_sink_capability()
3547 if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) in intel_psr_sink_capability()
3555 struct intel_psr *psr = &intel_dp->psr; in intel_psr_print_mode()
3558 if (psr->enabled) in intel_psr_print_mode()
3563 if (psr->panel_replay_enabled && psr->sel_update_enabled) in intel_psr_print_mode()
3565 else if (psr->panel_replay_enabled) in intel_psr_print_mode()
3567 else if (psr->sel_update_enabled) in intel_psr_print_mode()
3569 else if (psr->enabled) in intel_psr_print_mode()
3574 if (psr->su_region_et_enabled) in intel_psr_print_mode()
3585 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_status()
3586 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_status()
3587 struct intel_psr *psr = &intel_dp->psr; in intel_psr_status()
3594 if (!(psr->sink_support || psr->sink_panel_replay_support)) in intel_psr_status()
3597 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_psr_status()
3598 mutex_lock(&psr->lock); in intel_psr_status()
3602 if (!psr->enabled) { in intel_psr_status()
3603 seq_printf(m, "PSR sink not reliable: %s\n", in intel_psr_status()
3604 str_yes_no(psr->sink_not_reliable)); in intel_psr_status()
3609 if (psr->panel_replay_enabled) { in intel_psr_status()
3618 } else if (psr->sel_update_enabled) { in intel_psr_status()
3628 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) in intel_psr_status()
3633 psr->busy_frontbuffer_bits); in intel_psr_status()
3642 if (psr->debug & I915_PSR_DEBUG_IRQ) { in intel_psr_status()
3644 psr->last_entry_attempt); in intel_psr_status()
3645 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); in intel_psr_status()
3648 if (psr->sel_update_enabled) { in intel_psr_status()
3674 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); in intel_psr_status()
3678 mutex_unlock(&psr->lock); in intel_psr_status()
3679 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in intel_psr_status()
3686 struct intel_display *display = m->private; in i915_edp_psr_status_show()
3691 return -ENODEV; in i915_edp_psr_status_show()
3694 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_status_show()
3700 return -ENODEV; in i915_edp_psr_status_show()
3710 struct drm_i915_private *dev_priv = to_i915(display->drm); in i915_edp_psr_debug_set()
3713 int ret = -ENODEV; in i915_edp_psr_debug_set()
3718 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_debug_set()
3721 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); in i915_edp_psr_debug_set()
3723 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in i915_edp_psr_debug_set()
3728 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in i915_edp_psr_debug_set()
3741 return -ENODEV; in i915_edp_psr_debug_get()
3743 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_debug_get()
3747 *val = READ_ONCE(intel_dp->psr.debug); in i915_edp_psr_debug_get()
3751 return -ENODEV; in i915_edp_psr_debug_get()
3760 struct drm_minor *minor = display->drm->primary; in intel_psr_debugfs_register()
3762 debugfs_create_file("i915_edp_psr_debug", 0644, minor->debugfs_root, in intel_psr_debugfs_register()
3765 debugfs_create_file("i915_edp_psr_status", 0444, minor->debugfs_root, in intel_psr_debugfs_register()
3771 if (intel_dp->psr.panel_replay_enabled) in psr_mode_str()
3772 return "PANEL-REPLAY"; in psr_mode_str()
3773 else if (intel_dp->psr.enabled) in psr_mode_str()
3781 struct intel_connector *connector = m->private; in i915_psr_sink_status_show()
3788 "transition to inactive, capture and display, timing re-sync", in i915_psr_sink_status_show()
3798 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); in i915_psr_sink_status_show()
3799 return -ENODEV; in i915_psr_sink_status_show()
3802 if (connector->base.status != connector_status_connected) in i915_psr_sink_status_show()
3803 return -ENODEV; in i915_psr_sink_status_show()
3838 struct intel_connector *connector = m->private; in i915_psr_status_show()
3848 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_psr_connector_debugfs_add()
3849 struct dentry *root = connector->base.debugfs_entry; in intel_psr_connector_debugfs_add()
3852 if ((connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && in intel_psr_connector_debugfs_add()
3853 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) || in intel_psr_connector_debugfs_add()
3854 connector->mst_port) in intel_psr_connector_debugfs_add()