Lines Matching +full:power +full:- +full:on +full:- +full:delay
1 // SPDX-License-Identifier: MIT
30 struct drm_i915_private *i915 = to_i915(display->drm); in pps_name()
31 struct intel_pps *pps = &intel_dp->pps; in pps_name()
34 switch (pps->pps_pipe) { in pps_name()
46 MISSING_CASE(pps->pps_pipe); in pps_name()
50 switch (pps->pps_idx) { in pps_name()
56 MISSING_CASE(pps->pps_idx); in pps_name()
67 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_lock()
71 * See intel_pps_reset_all() why we need a power domain reference here. in intel_pps_lock()
74 mutex_lock(&display->pps.mutex); in intel_pps_lock()
83 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_unlock()
85 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
95 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_power_sequencer_kick()
97 enum pipe pipe = intel_dp->pps.pps_pipe; in vlv_power_sequencer_kick()
103 if (drm_WARN(display->drm, in vlv_power_sequencer_kick()
104 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
107 dig_port->base.base.base.id, dig_port->base.base.name)) in vlv_power_sequencer_kick()
110 drm_dbg_kms(display->drm, in vlv_power_sequencer_kick()
113 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_power_sequencer_kick()
115 /* Preserve the BIOS-computed detected bit. This is in vlv_power_sequencer_kick()
116 * supposed to be read-only. in vlv_power_sequencer_kick()
118 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
139 drm_err(display->drm, in vlv_power_sequencer_kick()
140 "Failed to force on PLL for pipe %c!\n", in vlv_power_sequencer_kick()
149 * to make this power sequencer lock onto the port. in vlv_power_sequencer_kick()
152 intel_de_write(display, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
153 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
155 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
156 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
158 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
159 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
175 * We don't have power sequencer currently. in vlv_find_free_pps()
178 for_each_intel_dp(display->drm, encoder) { in vlv_find_free_pps()
181 if (encoder->type == INTEL_OUTPUT_EDP) { in vlv_find_free_pps()
182 drm_WARN_ON(display->drm, in vlv_find_free_pps()
183 intel_dp->pps.active_pipe != INVALID_PIPE && in vlv_find_free_pps()
184 intel_dp->pps.active_pipe != in vlv_find_free_pps()
185 intel_dp->pps.pps_pipe); in vlv_find_free_pps()
187 if (intel_dp->pps.pps_pipe != INVALID_PIPE) in vlv_find_free_pps()
188 pipes &= ~(1 << intel_dp->pps.pps_pipe); in vlv_find_free_pps()
190 drm_WARN_ON(display->drm, in vlv_find_free_pps()
191 intel_dp->pps.pps_pipe != INVALID_PIPE); in vlv_find_free_pps()
193 if (intel_dp->pps.active_pipe != INVALID_PIPE) in vlv_find_free_pps()
194 pipes &= ~(1 << intel_dp->pps.active_pipe); in vlv_find_free_pps()
201 return ffs(pipes) - 1; in vlv_find_free_pps()
211 lockdep_assert_held(&display->pps.mutex); in vlv_power_sequencer_pipe()
214 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in vlv_power_sequencer_pipe()
216 drm_WARN_ON(display->drm, intel_dp->pps.active_pipe != INVALID_PIPE && in vlv_power_sequencer_pipe()
217 intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe); in vlv_power_sequencer_pipe()
219 if (intel_dp->pps.pps_pipe != INVALID_PIPE) in vlv_power_sequencer_pipe()
220 return intel_dp->pps.pps_pipe; in vlv_power_sequencer_pipe()
226 * are two power sequencers and up to two eDP ports. in vlv_power_sequencer_pipe()
228 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE)) in vlv_power_sequencer_pipe()
232 intel_dp->pps.pps_pipe = pipe; in vlv_power_sequencer_pipe()
234 drm_dbg_kms(display->drm, in vlv_power_sequencer_pipe()
237 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_power_sequencer_pipe()
239 /* init power sequencer on this pipe and port */ in vlv_power_sequencer_pipe()
245 * the power sequencer lock in on the port. in vlv_power_sequencer_pipe()
249 return intel_dp->pps.pps_pipe; in vlv_power_sequencer_pipe()
256 int pps_idx = intel_dp->pps.pps_idx; in bxt_power_sequencer_idx()
258 lockdep_assert_held(&display->pps.mutex); in bxt_power_sequencer_idx()
261 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in bxt_power_sequencer_idx()
263 if (!intel_dp->pps.pps_reset) in bxt_power_sequencer_idx()
266 intel_dp->pps.pps_reset = false; in bxt_power_sequencer_idx()
322 enum port port = dig_port->base.port; in vlv_initial_power_sequencer_setup()
324 lockdep_assert_held(&display->pps.mutex); in vlv_initial_power_sequencer_setup()
327 /* first pick one where the panel is on */ in vlv_initial_power_sequencer_setup()
328 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
330 /* didn't find one? pick one where vdd is on */ in vlv_initial_power_sequencer_setup()
331 if (intel_dp->pps.pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
332 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
335 if (intel_dp->pps.pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
336 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
340 if (intel_dp->pps.pps_pipe == INVALID_PIPE) { in vlv_initial_power_sequencer_setup()
341 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
342 "[ENCODER:%d:%s] no initial power sequencer\n", in vlv_initial_power_sequencer_setup()
343 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_initial_power_sequencer_setup()
347 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
348 "[ENCODER:%d:%s] initial power sequencer: %s\n", in vlv_initial_power_sequencer_setup()
349 dig_port->base.base.base.id, dig_port->base.base.name, in vlv_initial_power_sequencer_setup()
355 struct drm_i915_private *i915 = to_i915(display->drm); in intel_num_pps()
378 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_is_valid()
380 if (intel_dp->pps.pps_idx == 1 && in intel_pps_is_valid()
398 return -1; in bxt_initial_pps_idx()
405 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in pps_initial_setup()
406 struct intel_connector *connector = intel_dp->attached_connector; in pps_initial_setup()
407 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in pps_initial_setup()
409 lockdep_assert_held(&display->pps.mutex); in pps_initial_setup()
418 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_initial_setup()
420 intel_dp->pps.pps_idx = 0; in pps_initial_setup()
422 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display))) in pps_initial_setup()
423 intel_dp->pps.pps_idx = -1; in pps_initial_setup()
425 /* VBT wasn't parsed yet? pick one where the panel is on */ in pps_initial_setup()
426 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
427 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on); in pps_initial_setup()
428 /* didn't find one? pick one where vdd is on */ in pps_initial_setup()
429 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
430 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on); in pps_initial_setup()
432 if (intel_dp->pps.pps_idx < 0) { in pps_initial_setup()
433 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any); in pps_initial_setup()
435 drm_dbg_kms(display->drm, in pps_initial_setup()
436 "[ENCODER:%d:%s] no initial power sequencer, assuming %s\n", in pps_initial_setup()
437 encoder->base.base.id, encoder->base.name, in pps_initial_setup()
440 drm_dbg_kms(display->drm, in pps_initial_setup()
441 "[ENCODER:%d:%s] initial power sequencer: %s\n", in pps_initial_setup()
442 encoder->base.base.id, encoder->base.name, in pps_initial_setup()
451 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_reset_all()
454 if (drm_WARN_ON(display->drm, !IS_LP(dev_priv))) in intel_pps_reset_all()
464 * hold both a power domain reference and pps_mutex, and the power domain in intel_pps_reset_all()
470 for_each_intel_dp(display->drm, encoder) { in intel_pps_reset_all()
473 drm_WARN_ON(display->drm, in intel_pps_reset_all()
474 intel_dp->pps.active_pipe != INVALID_PIPE); in intel_pps_reset_all()
476 if (encoder->type != INTEL_OUTPUT_EDP) in intel_pps_reset_all()
480 intel_dp->pps.pps_reset = true; in intel_pps_reset_all()
482 intel_dp->pps.pps_pipe = INVALID_PIPE; in intel_pps_reset_all()
498 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_get_registers()
508 pps_idx = intel_dp->pps.pps_idx; in intel_pps_get_registers()
510 regs->pp_ctrl = PP_CONTROL(display, pps_idx); in intel_pps_get_registers()
511 regs->pp_stat = PP_STATUS(display, pps_idx); in intel_pps_get_registers()
512 regs->pp_on = PP_ON_DELAYS(display, pps_idx); in intel_pps_get_registers()
513 regs->pp_off = PP_OFF_DELAYS(display, pps_idx); in intel_pps_get_registers()
515 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ in intel_pps_get_registers()
518 regs->pp_div = INVALID_MMIO_REG; in intel_pps_get_registers()
520 regs->pp_div = PP_DIVISOR(display, pps_idx); in intel_pps_get_registers()
546 struct drm_i915_private *dev_priv = to_i915(display->drm); in edp_have_panel_power()
548 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_power()
551 intel_dp->pps.pps_pipe == INVALID_PIPE) in edp_have_panel_power()
560 struct drm_i915_private *dev_priv = to_i915(display->drm); in edp_have_panel_vdd()
562 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_vdd()
565 intel_dp->pps.pps_pipe == INVALID_PIPE) in edp_have_panel_vdd()
580 drm_WARN(display->drm, 1, in intel_pps_check_power_unlocked()
582 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_check_power_unlocked()
584 drm_dbg_kms(display->drm, in intel_pps_check_power_unlocked()
586 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_check_power_unlocked()
611 lockdep_assert_held(&display->pps.mutex); in wait_panel_status()
618 drm_dbg_kms(display->drm, in wait_panel_status()
620 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_status()
627 drm_err(display->drm, in wait_panel_status()
629 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_status()
634 drm_dbg_kms(display->drm, "Wait complete\n"); in wait_panel_status()
642 drm_dbg_kms(display->drm, in wait_panel_on()
643 "[ENCODER:%d:%s] %s wait for panel power on\n", in wait_panel_on()
644 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_on()
654 drm_dbg_kms(display->drm, in wait_panel_off()
655 "[ENCODER:%d:%s] %s wait for panel power off time\n", in wait_panel_off()
656 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_off()
668 drm_dbg_kms(display->drm, in wait_panel_power_cycle()
669 "[ENCODER:%d:%s] %s wait for panel power cycle\n", in wait_panel_power_cycle()
670 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_power_cycle()
673 /* take the difference of current time and panel power off time in wait_panel_power_cycle()
676 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); in wait_panel_power_cycle()
680 if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay) in wait_panel_power_cycle()
682 intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); in wait_panel_power_cycle()
700 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on, in wait_backlight_on()
701 intel_dp->pps.backlight_on_delay); in wait_backlight_on()
706 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off, in edp_wait_backlight_off()
707 intel_dp->pps.backlight_off_delay); in edp_wait_backlight_off()
719 lockdep_assert_held(&display->pps.mutex); in ilk_get_pp_control()
722 if (drm_WARN_ON(display->drm, !HAS_DDI(display) && in ilk_get_pp_control()
732 * Must hold pps_mutex around the whole on/off sequence.
733 * Can be nested with intel_pps_vdd_{on,off}() calls.
738 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_vdd_on_unlocked()
742 bool need_to_disable = !intel_dp->pps.want_panel_vdd; in intel_pps_vdd_on_unlocked()
744 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_on_unlocked()
749 cancel_delayed_work(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_on_unlocked()
750 intel_dp->pps.want_panel_vdd = true; in intel_pps_vdd_on_unlocked()
755 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_on_unlocked()
756 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, in intel_pps_vdd_on_unlocked()
762 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n", in intel_pps_vdd_on_unlocked()
763 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
774 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
776 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
781 * If the panel wasn't on, delay before accessing aux channel in intel_pps_vdd_on_unlocked()
784 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
785 "[ENCODER:%d:%s] %s panel power wasn't enabled\n", in intel_pps_vdd_on_unlocked()
786 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
788 msleep(intel_dp->pps.panel_power_up_delay); in intel_pps_vdd_on_unlocked()
803 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_vdd_on()
813 I915_STATE_WARN(i915, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", in intel_pps_vdd_on()
814 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_on()
815 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_vdd_on()
822 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_vdd_off_sync_unlocked()
827 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_sync_unlocked()
829 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd); in intel_pps_vdd_off_sync_unlocked()
834 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n", in intel_pps_vdd_off_sync_unlocked()
835 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_off_sync_unlocked()
848 drm_dbg_kms(display->drm, in intel_pps_vdd_off_sync_unlocked()
850 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_off_sync_unlocked()
856 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_vdd_off_sync_unlocked()
860 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_vdd_off_sync_unlocked()
870 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_off_sync()
887 if (!intel_dp->pps.want_panel_vdd) in edp_panel_vdd_work()
895 struct drm_i915_private *i915 = to_i915(display->drm); in edp_panel_vdd_schedule_off()
896 unsigned long delay; in edp_panel_vdd_schedule_off() local
899 * We may not yet know the real power sequencing delays, in edp_panel_vdd_schedule_off()
902 if (intel_dp->pps.initializing) in edp_panel_vdd_schedule_off()
906 * Queue the timer to fire a long time from now (relative to the power in edp_panel_vdd_schedule_off()
907 * down delay) to keep the panel power up across a sequence of in edp_panel_vdd_schedule_off()
910 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5); in edp_panel_vdd_schedule_off()
911 queue_delayed_work(i915->unordered_wq, in edp_panel_vdd_schedule_off()
912 &intel_dp->pps.panel_vdd_work, delay); in edp_panel_vdd_schedule_off()
917 * Must hold pps_mutex around the whole on/off sequence.
918 * Can be nested with intel_pps_vdd_{on,off}() calls.
923 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_vdd_off_unlocked()
925 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_unlocked()
930 I915_STATE_WARN(dev_priv, !intel_dp->pps.want_panel_vdd, in intel_pps_vdd_off_unlocked()
931 "[ENCODER:%d:%s] %s VDD not forced on", in intel_pps_vdd_off_unlocked()
932 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_off_unlocked()
933 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_vdd_off_unlocked()
936 intel_dp->pps.want_panel_vdd = false; in intel_pps_vdd_off_unlocked()
947 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_on_unlocked()
951 lockdep_assert_held(&display->pps.mutex); in intel_pps_on_unlocked()
956 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n", in intel_pps_on_unlocked()
957 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
958 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_on_unlocked()
961 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp), in intel_pps_on_unlocked()
962 "[ENCODER:%d:%s] %s panel power already on\n", in intel_pps_on_unlocked()
963 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
964 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_on_unlocked()
973 /* ILK workaround: disable reset around power sequence */ in intel_pps_on_unlocked()
981 * Disable DPLS gating around power sequence. in intel_pps_on_unlocked()
995 intel_dp->pps.last_power_on = jiffies; in intel_pps_on_unlocked()
1022 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_off_unlocked()
1027 lockdep_assert_held(&display->pps.mutex); in intel_pps_off_unlocked()
1032 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n", in intel_pps_off_unlocked()
1033 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_off_unlocked()
1036 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd, in intel_pps_off_unlocked()
1038 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_off_unlocked()
1042 /* We need to switch off panel power _and_ force vdd, for otherwise some in intel_pps_off_unlocked()
1049 intel_dp->pps.want_panel_vdd = false; in intel_pps_off_unlocked()
1055 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_off_unlocked()
1060 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_off_unlocked()
1074 /* Enable backlight in the panel power control. */
1081 * If we enable the backlight right away following a panel power in intel_pps_backlight_on()
1082 * on, we may see slight flicker as the panel syncs with the eDP in intel_pps_backlight_on()
1083 * link. So delay a bit to make sure the image is solid before in intel_pps_backlight_on()
1100 /* Disable backlight in the panel power control. */
1120 intel_dp->pps.last_backlight_off = jiffies; in intel_pps_backlight_off()
1125 * Hook for controlling the panel power control backlight through the bl_power
1141 drm_dbg_kms(display->drm, "panel power control backlight %s\n", in intel_pps_backlight_power()
1154 enum pipe pipe = intel_dp->pps.pps_pipe; in vlv_detach_power_sequencer()
1157 drm_WARN_ON(display->drm, intel_dp->pps.active_pipe != INVALID_PIPE); in vlv_detach_power_sequencer()
1159 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1165 * VLV seems to get confused when multiple power sequencers in vlv_detach_power_sequencer()
1166 * have the same port selected (even if only one has power/vdd in vlv_detach_power_sequencer()
1168 * CHV on the other hand doesn't seem to mind having the same port in vlv_detach_power_sequencer()
1169 * selected in multiple power sequencers, but let's clear the in vlv_detach_power_sequencer()
1170 * port select always when logically disconnecting a power sequencer in vlv_detach_power_sequencer()
1173 drm_dbg_kms(display->drm, in vlv_detach_power_sequencer()
1176 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_detach_power_sequencer()
1180 intel_dp->pps.pps_pipe = INVALID_PIPE; in vlv_detach_power_sequencer()
1188 lockdep_assert_held(&display->pps.mutex); in vlv_steal_power_sequencer()
1190 for_each_intel_dp(display->drm, encoder) { in vlv_steal_power_sequencer()
1193 drm_WARN(display->drm, intel_dp->pps.active_pipe == pipe, in vlv_steal_power_sequencer()
1195 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
1196 encoder->base.name); in vlv_steal_power_sequencer()
1198 if (intel_dp->pps.pps_pipe != pipe) in vlv_steal_power_sequencer()
1201 drm_dbg_kms(display->drm, in vlv_steal_power_sequencer()
1203 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
1204 encoder->base.name); in vlv_steal_power_sequencer()
1216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_pps_init()
1218 lockdep_assert_held(&display->pps.mutex); in vlv_pps_init()
1220 drm_WARN_ON(display->drm, intel_dp->pps.active_pipe != INVALID_PIPE); in vlv_pps_init()
1222 if (intel_dp->pps.pps_pipe != INVALID_PIPE && in vlv_pps_init()
1223 intel_dp->pps.pps_pipe != crtc->pipe) { in vlv_pps_init()
1225 * If another power sequencer was being used on this in vlv_pps_init()
1233 * We may be stealing the power in vlv_pps_init()
1236 vlv_steal_power_sequencer(display, crtc->pipe); in vlv_pps_init()
1238 intel_dp->pps.active_pipe = crtc->pipe; in vlv_pps_init()
1244 intel_dp->pps.pps_pipe = crtc->pipe; in vlv_pps_init()
1246 drm_dbg_kms(display->drm, in vlv_pps_init()
1249 encoder->base.base.id, encoder->base.name); in vlv_pps_init()
1251 /* init power sequencer on this pipe and port */ in vlv_pps_init()
1259 struct drm_i915_private *dev_priv = to_i915(display->drm); in pps_vdd_init()
1262 lockdep_assert_held(&display->pps.mutex); in pps_vdd_init()
1268 * The VDD bit needs a power domain reference, so if the bit is in pps_vdd_init()
1270 * schedule a vdd off, so we don't hold on to the reference in pps_vdd_init()
1273 drm_dbg_kms(display->drm, in pps_vdd_init()
1274 "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n", in pps_vdd_init()
1275 dig_port->base.base.base.id, dig_port->base.base.name, in pps_vdd_init()
1277 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in pps_vdd_init()
1278 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, in pps_vdd_init()
1298 * Initialize panel power off time to 0, assuming panel power could have in pps_init_timestamps()
1300 * and removed i915, which has already ensured sufficient power off in pps_init_timestamps()
1301 * delay at module remove. in pps_init_timestamps()
1303 intel_dp->pps.panel_power_off_time = 0; in pps_init_timestamps()
1304 intel_dp->pps.last_power_on = jiffies; in pps_init_timestamps()
1305 intel_dp->pps.last_backlight_off = jiffies; in pps_init_timestamps()
1327 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1328 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1329 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1330 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1337 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1339 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
1349 drm_dbg_kms(display->drm, in intel_pps_dump_state()
1352 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1360 struct edp_power_seq *sw = &intel_dp->pps.pps_delays; in intel_pps_verify_state()
1364 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
1365 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { in intel_pps_verify_state()
1366 drm_err(display->drm, "PPS state mismatch\n"); in intel_pps_verify_state()
1374 return delays->t1_t3 || delays->t8 || delays->t9 || in pps_delays_valid()
1375 delays->t10 || delays->t11_t12; in pps_delays_valid()
1383 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_bios()
1385 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays)) in pps_init_delays_bios()
1386 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays); in pps_init_delays_bios()
1388 *bios = intel_dp->pps.bios_pps_delays; in pps_init_delays_bios()
1397 struct intel_connector *connector = intel_dp->attached_connector; in pps_init_delays_vbt()
1399 *vbt = connector->panel.vbt.edp.pps; in pps_init_delays_vbt()
1404 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay in pps_init_delays_vbt()
1406 * just fails to power back on. Increasing the delay to 800ms in pps_init_delays_vbt()
1410 vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10); in pps_init_delays_vbt()
1411 drm_dbg_kms(display->drm, in pps_init_delays_vbt()
1412 "Increasing T12 panel delay as per the quirk to %d\n", in pps_init_delays_vbt()
1413 vbt->t11_t12); in pps_init_delays_vbt()
1416 /* T11_T12 delay is special and actually in units of 100ms, but zero in pps_init_delays_vbt()
1420 vbt->t11_t12 += 100 * 10; in pps_init_delays_vbt()
1430 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_spec()
1434 spec->t1_t3 = 210 * 10; in pps_init_delays_spec()
1435 spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */ in pps_init_delays_spec()
1436 spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ in pps_init_delays_spec()
1437 spec->t10 = 500 * 10; in pps_init_delays_spec()
1442 spec->t11_t12 = (510 + 100) * 10; in pps_init_delays_spec()
1451 *final = &intel_dp->pps.pps_delays; in pps_init_delays()
1453 lockdep_assert_held(&display->pps.mutex); in pps_init_delays()
1465 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ in pps_init_delays()
1475 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) in pps_init_delays()
1476 intel_dp->pps.panel_power_up_delay = get_delay(t1_t3); in pps_init_delays()
1477 intel_dp->pps.backlight_on_delay = get_delay(t8); in pps_init_delays()
1478 intel_dp->pps.backlight_off_delay = get_delay(t9); in pps_init_delays()
1479 intel_dp->pps.panel_power_down_delay = get_delay(t10); in pps_init_delays()
1480 intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12); in pps_init_delays()
1483 drm_dbg_kms(display->drm, in pps_init_delays()
1484 "panel power up delay %d, power down delay %d, power cycle delay %d\n", in pps_init_delays()
1485 intel_dp->pps.panel_power_up_delay, in pps_init_delays()
1486 intel_dp->pps.panel_power_down_delay, in pps_init_delays()
1487 intel_dp->pps.panel_power_cycle_delay); in pps_init_delays()
1489 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n", in pps_init_delays()
1490 intel_dp->pps.backlight_on_delay, in pps_init_delays()
1491 intel_dp->pps.backlight_off_delay); in pps_init_delays()
1495 * on them. For T8, even BSpec recommends doing it. For T9, if we in pps_init_delays()
1496 * don't do this, we'll end up waiting for the backlight off delay in pps_init_delays()
1500 final->t8 = 1; in pps_init_delays()
1501 final->t9 = 1; in pps_init_delays()
1507 final->t11_t12 = roundup(final->t11_t12, 100 * 10); in pps_init_delays()
1513 struct drm_i915_private *dev_priv = to_i915(display->drm); in pps_init_registers()
1515 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000; in pps_init_registers()
1517 enum port port = dp_to_dig_port(intel_dp)->base.port; in pps_init_registers()
1518 const struct edp_power_seq *seq = &intel_dp->pps.pps_delays; in pps_init_registers()
1520 lockdep_assert_held(&display->pps.mutex); in pps_init_registers()
1525 * On some VLV machines the BIOS can leave the VDD in pps_init_registers()
1526 * enabled even on power sequencers which aren't in pps_init_registers()
1528 * power domain tracking the first time we pick in pps_init_registers()
1529 * one of these power sequencers for use since in pps_init_registers()
1531 * already on and therefore wouldn't grab the power in pps_init_registers()
1533 * This also avoids spuriously turning the VDD on as in pps_init_registers()
1534 * soon as the new power sequencer gets initialized. in pps_init_registers()
1539 drm_WARN(display->drm, pp & PANEL_POWER_ON, in pps_init_registers()
1540 "Panel power already on\n"); in pps_init_registers()
1543 drm_dbg_kms(display->drm, in pps_init_registers()
1544 "VDD already on, disabling first\n"); in pps_init_registers()
1551 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in pps_init_registers()
1552 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in pps_init_registers()
1553 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in pps_init_registers()
1554 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in pps_init_registers()
1557 * power sequencer any more. */ in pps_init_registers()
1587 …P_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_… in pps_init_registers()
1591 DIV_ROUND_UP(seq->t11_t12, 1000))); in pps_init_registers()
1593 drm_dbg_kms(display->drm, in pps_init_registers()
1594 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", in pps_init_registers()
1605 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_encoder_reset()
1613 * Reinit the power sequencer also on the resume path, in case in intel_pps_encoder_reset()
1633 intel_dp->pps.initializing = true; in intel_pps_init()
1634 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); in intel_pps_init()
1652 struct drm_i915_private *i915 = to_i915(display->drm); in pps_init_late()
1653 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in pps_init_late()
1654 struct intel_connector *connector = intel_dp->attached_connector; in pps_init_late()
1662 drm_WARN(display->drm, in pps_init_late()
1663 connector->panel.vbt.backlight.controller >= 0 && in pps_init_late()
1664 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller, in pps_init_late()
1665 "[ENCODER:%d:%s] power sequencer mismatch: %d (initial) vs. %d (VBT)\n", in pps_init_late()
1666 encoder->base.base.id, encoder->base.name, in pps_init_late()
1667 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller); in pps_init_late()
1669 if (connector->panel.vbt.backlight.controller >= 0) in pps_init_late()
1670 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_init_late()
1678 /* Reinit delays after per-panel info has been parsed from VBT */ in intel_pps_init_late()
1681 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays)); in intel_pps_init_late()
1685 intel_dp->pps.initializing = false; in intel_pps_init_late()
1700 * This w/a is needed at least on CPT/PPT, but to be sure apply it in intel_pps_unlock_regs_wa()
1712 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_setup()
1715 display->pps.mmio_base = PCH_PPS_BASE; in intel_pps_setup()
1717 display->pps.mmio_base = VLV_PPS_BASE; in intel_pps_setup()
1719 display->pps.mmio_base = PPS_BASE; in intel_pps_setup()
1724 struct intel_connector *connector = m->private; in intel_pps_show()
1727 if (connector->base.status != connector_status_connected) in intel_pps_show()
1728 return -ENODEV; in intel_pps_show()
1730 seq_printf(m, "Panel power up delay: %d\n", in intel_pps_show()
1731 intel_dp->pps.panel_power_up_delay); in intel_pps_show()
1732 seq_printf(m, "Panel power down delay: %d\n", in intel_pps_show()
1733 intel_dp->pps.panel_power_down_delay); in intel_pps_show()
1734 seq_printf(m, "Backlight on delay: %d\n", in intel_pps_show()
1735 intel_dp->pps.backlight_on_delay); in intel_pps_show()
1736 seq_printf(m, "Backlight off delay: %d\n", in intel_pps_show()
1737 intel_dp->pps.backlight_off_delay); in intel_pps_show()
1745 struct dentry *root = connector->base.debugfs_entry; in intel_pps_connector_debugfs_add()
1746 int connector_type = connector->base.connector_type; in intel_pps_connector_debugfs_add()
1755 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_pps_unlocked()
1761 if (drm_WARN_ON(display->drm, HAS_DDI(display))) in assert_pps_unlocked()
1789 /* presumably write lock depends on pipe, not port select */ in assert_pps_unlocked()
1799 drm_WARN_ON(display->drm, in assert_pps_unlocked()