Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: MIT
19 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy()
25 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy()
111 mutex_lock(&dev_priv->sb_lock); in lpt_disable_iclkip()
117 mutex_unlock(&dev_priv->sb_lock); in lpt_disable_iclkip()
130 p->iclk_virtual_root_freq = 172800 * 1000; in iclkip_params_init()
131 p->iclk_pi_range = 64; in iclkip_params_init()
136 return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_iclkip_freq()
137 p->desired_divisor << p->auxdiv); in lpt_iclkip_freq()
145 * but the adjusted_mode->crtc_clock in KHz. To get the in lpt_compute_iclkip()
150 for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) { in lpt_compute_iclkip()
151 p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_compute_iclkip()
152 clock << p->auxdiv); in lpt_compute_iclkip()
153 p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2; in lpt_compute_iclkip()
154 p->phaseinc = p->desired_divisor % p->iclk_pi_range; in lpt_compute_iclkip()
158 * out of range for the 7-bit divisor in lpt_compute_iclkip()
160 if (p->divsel <= 0x7f) in lpt_compute_iclkip()
169 lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock); in lpt_iclkip()
177 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in lpt_program_iclkip()
178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in lpt_program_iclkip()
179 int clock = crtc_state->hw.adjusted_mode.crtc_clock; in lpt_program_iclkip()
186 drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock); in lpt_program_iclkip()
189 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) & in lpt_program_iclkip()
191 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) & in lpt_program_iclkip()
194 drm_dbg_kms(&dev_priv->drm, in lpt_program_iclkip()
198 mutex_lock(&dev_priv->sb_lock); in lpt_program_iclkip()
216 /* Enable modulator and associated divider */ in lpt_program_iclkip()
221 mutex_unlock(&dev_priv->sb_lock); in lpt_program_iclkip()
239 mutex_lock(&dev_priv->sb_lock); in lpt_get_iclkip()
243 mutex_unlock(&dev_priv->sb_lock); in lpt_get_iclkip()
257 mutex_unlock(&dev_priv->sb_lock); in lpt_get_iclkip()
266 * - Sequence to enable CLKOUT_DP
267 * - Sequence to enable CLKOUT_DP without spread
268 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
275 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread, in lpt_enable_clkout_dp()
278 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && in lpt_enable_clkout_dp()
282 mutex_lock(&dev_priv->sb_lock); in lpt_enable_clkout_dp()
305 mutex_unlock(&dev_priv->sb_lock); in lpt_enable_clkout_dp()
313 mutex_lock(&dev_priv->sb_lock); in lpt_disable_clkout_dp()
331 mutex_unlock(&dev_priv->sb_lock); in lpt_disable_clkout_dp()
348 [BEND_IDX( -5)] = 0x0025,
349 [BEND_IDX(-10)] = 0x0125,
350 [BEND_IDX(-15)] = 0x0125,
351 [BEND_IDX(-20)] = 0x0225,
352 [BEND_IDX(-25)] = 0x0225,
353 [BEND_IDX(-30)] = 0x0325,
354 [BEND_IDX(-35)] = 0x0325,
355 [BEND_IDX(-40)] = 0x0425,
356 [BEND_IDX(-45)] = 0x0425,
357 [BEND_IDX(-50)] = 0x0525,
362 * steps -50 to 50 inclusive, in steps of 5
364 * change in clock period = -(steps / 10) * 5.787 ps
371 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0)) in lpt_bend_clkout_dp()
374 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))) in lpt_bend_clkout_dp()
377 mutex_lock(&dev_priv->sb_lock); in lpt_bend_clkout_dp()
390 mutex_unlock(&dev_priv->sb_lock); in lpt_bend_clkout_dp()
439 for_each_intel_encoder(&dev_priv->drm, encoder) { in lpt_init_pch_refclk()
440 switch (encoder->type) { in lpt_init_pch_refclk()
450 * The BIOS may have decided to use the PCH SSC in lpt_init_pch_refclk()
453 * just leave the PCH SSC reference enabled in case in lpt_init_pch_refclk()
459 * actually enable/disable/reconfigure these things in lpt_init_pch_refclk()
464 dev_priv->display.dpll.pch_ssc_use = 0; in lpt_init_pch_refclk()
467 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n"); in lpt_init_pch_refclk()
468 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL); in lpt_init_pch_refclk()
472 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n"); in lpt_init_pch_refclk()
473 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1); in lpt_init_pch_refclk()
477 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n"); in lpt_init_pch_refclk()
478 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2); in lpt_init_pch_refclk()
481 if (dev_priv->display.dpll.pch_ssc_use) in lpt_init_pch_refclk()
506 for_each_intel_encoder(&dev_priv->drm, encoder) { in ilk_init_pch_refclk()
507 switch (encoder->type) { in ilk_init_pch_refclk()
514 if (encoder->port == PORT_A) in ilk_init_pch_refclk()
523 has_ck505 = dev_priv->display.vbt.display_clock_mode; in ilk_init_pch_refclk()
530 /* Check if any DPLLs are using the SSC source */ in ilk_init_pch_refclk()
534 temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id)); in ilk_init_pch_refclk()
546 drm_dbg_kms(&dev_priv->drm, in ilk_init_pch_refclk()
557 /* As we must carefully and slowly disable/enable each source in turn, in ilk_init_pch_refclk()
594 /* Always enable nonspread source */ in ilk_init_pch_refclk()
606 /* SSC must be turned on before enabling the CPU output */ in ilk_init_pch_refclk()
608 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n"); in ilk_init_pch_refclk()
614 /* Get SSC going before enabling the outputs */ in ilk_init_pch_refclk()
621 /* Enable CPU source on CPU attached eDP */ in ilk_init_pch_refclk()
624 drm_dbg_kms(&dev_priv->drm, in ilk_init_pch_refclk()
625 "Using SSC on eDP\n"); in ilk_init_pch_refclk()
638 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n"); in ilk_init_pch_refclk()
650 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n"); in ilk_init_pch_refclk()
652 /* Turn off the SSC source */ in ilk_init_pch_refclk()
665 drm_WARN_ON(&dev_priv->drm, val != final); in ilk_init_pch_refclk()